公开(公告)号：US10790154B2

公开(公告)日：2020-09-29

申请号：US16269252

申请日：2019-02-06

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/67 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238

Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.

公开(公告)号：US10734228B2

公开(公告)日：2020-08-04

申请号：US16212144

申请日：2018-12-06

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  David L. O'Meara

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/00 ,  H01L21/02 ,  H01L21/308

Abstract: Embodiments are disclosed for processing microelectronic workpieces to apply stress engineering to self-aligned multi-patterning (SAMP) processes. The disclosed processing methods utilize stress in a substrate in a SAMP process to improve resulting pattern parameters. Initially, a high stress film is deposited on the frontside and the backside of the substrate, and the high stress film provides biaxial stress to the substrate due to the deposition process for the high stress film. Next, a SAMP process is performed to form spacers in a spacer pattern. This spacer pattern is then transferred to underlying layers to form a patterned structure. The high stress film provides axial stress in at least one direction along a portion of the patterned structure during the pattern transfer thereby improving resulting pattern formation.

公开(公告)号：US20200013590A1

公开(公告)日：2020-01-09

申请号：US16460730

申请日：2019-07-02

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

IPC: H01J37/32 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/687

Abstract: Embodiments are described herein to reduce formation of undesired particles during plasma processing for microelectronic workpieces by depositing a layer (e.g., think film) on the surface of a chuck, such as an electrostatic chuck (ESC), prior to plasma processing such as a plasma etch process (e.g., a reactive ion etch (RIE) process) and/or a plasma deposition process. This layer works as a lubricant or protective coating to reduce or minimize physical contact between the microelectronic workpiece (e.g., semiconductor wafer) and the chuck. This reduction in physical contact reduces scratching of the backside of the microelectronic workpiece and reduces related formation of undesired particles that can be transported to the front side of the microelectronic workpiece and cause defects and reduce yields. As such, the disclosed embodiments improve particle (PA) performance parameters for plasma etch and/or deposition processes.

公开(公告)号：US10354873B2

公开(公告)日：2019-07-16

申请号：US15491432

申请日：2017-04-19

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko ,  Angelique Raley ,  Sophie Thibaut ,  Satoru Nakamura ,  Nihar Mohanty

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/66

Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

公开(公告)号：US10217670B2

公开(公告)日：2019-02-26

申请号：US15697249

申请日：2017-09-06

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Satoru Nakamura ,  Soo Doo Chae ,  Akiteru Ko ,  Kaoru Maekawa ,  Gerrit J. Leusink

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

公开(公告)号：US20180068899A1

公开(公告)日：2018-03-08

申请号：US15697249

申请日：2017-09-06

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Satoru Nakamura ,  Soo Doo Chae ,  Akiteru Ko ,  Kaoru Maekawa ,  Gerrit J. Leusink

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

公开(公告)号：US20170243744A1

公开(公告)日：2017-08-24

申请号：US15232330

申请日：2016-08-09

Applicant: Tokyo Electron Limited

Inventor： Vinh Luong ,  Akiteru Ko

IPC: H01L21/033 ,  H01L21/683 ,  H01L21/66 ,  H01L21/311

CPC classification number: H01L21/0337 ,  G03F7/0043 ,  G03F7/094 ,  G03F7/405 ,  H01J2237/3342 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/32139 ,  H01L21/67017 ,  H01L21/67109 ,  H01L21/6831 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: Provided is a method of trimming an inorganic resist in an integration scheme, the method comprising: disposing a substrate in a process chamber, the substrate having an inorganic resist layer and an underlying layer comprising an oxide layer, a silicon nitride layer, and a base layer, the inorganic resist layer having an inorganic structure pattern; performing an inorganic resist trimming process to selectively remove a portion of the inorganic resist structure pattern on the substrate, the trimming process using a first etchant gas mixture and generating a first pattern; controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives; wherein the first etchant gas mixture comprises a fluorine-containing gas and a diluent gas; and wherein the target integration objectives include a target critical dimension (CD), a target line edge roughness (LER), a target line width roughness (LWR) and a target substrate throughput.

公开(公告)号：US09697990B2

公开(公告)日：2017-07-04

申请号：US15352112

申请日：2016-11-15

Applicant: Tokyo Electron Limited

Inventor： Satoru Nakamura ,  Akiteru Ko

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67

CPC classification number: H01J37/32082 ,  H01J37/32192 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32724 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/67069 ,  H01L22/12 ,  H01L22/20

Abstract: Provided is a method of plasma etching on a substrate using an etchant gas mixture to meet integration objectives, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material and the underlying layer comprising a silicon anti-reflective (SiARC) layer, a spin-on carbon hardmask (CHM) layer, an oxide layer, and a target layer; performing an first etch process to selectively remove the second material and the neutral layer using a first etchant gas mixture to form a first pattern; performing an second etch process to selectively remove the SiARC layer to form a second pattern; performing an third etch process to selectively remove the CHM layer to form a third pattern; concurrently controlling selected two or more operating variables wherein the first etchant gas include oxygen and sulfur-containing gases.

公开(公告)号：US20170154781A1

公开(公告)日：2017-06-01

申请号：US15431049

申请日：2017-02-13

Applicant: Tokyo Electron Limited

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  H01L21/311 ,  H01L29/51

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

公开(公告)号：US20160300718A1

公开(公告)日：2016-10-13

申请号：US15089961

申请日：2016-04-04

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Nihar Mohanty ,  Akiteru Ko

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/02186 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.

Abstract translation: 提供了一种使用积分方案提高结构的图案密度并且在不使用硬心轴的情况下在抗蚀剂层处进行间距分割的方法，所述方法包括：提供具有图案化抗蚀剂层的基底和包含硅抗蚀剂的下层 反射涂层，非晶层和靶层; 进行抗蚀剂硬化处理; 使用具有氧化物的原子层沉积技术执行第一共形间隔物沉积，在所述第一共形层上执行间隔物第一反应离子蚀刻工艺和第一拉伸工艺，使用氧化钛执行第二共形间隔物沉积; 执行第二间隔RIE处理和第二拉伸处理，产生第二间隔图案; 并且将第二间隔图案转移到目标层中，其中靶包括图案均匀性，结构的下拉，结构的减薄，结构的纵横比和线宽粗糙度。