公开(公告)号：US09748110B2

公开(公告)日：2017-08-29

申请号：US15247138

申请日：2016-08-25

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Angelique D. Raley ,  Nihar Mohanty ,  Aelan Mosden

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

公开(公告)号：US20160379842A1

公开(公告)日：2016-12-29

申请号：US15191956

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67248

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

Abstract translation: 描述了用于干燥去除微电子工件上的材料的方法。 该方法包括接收具有暴露由硅构成的目标层的表面和（1）有机材料或（2）氧和氮两者的表面的工件，并且从工件中选择性地去除目标层的至少一部分。 选择性去除包括将工件的表面暴露于含有N，H和F的化学环境处于第一设定点温度以化学改变目标层的表面区域，然后将工件的温度升高到第二设定点 温度以去除目标层的化学处理的表面区域。

公开(公告)号：US09165765B1

公开(公告)日：2015-10-20

申请号：US14481136

申请日：2014-09-09

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Akiteru Ko

IPC: H01L21/4763 ,  H01L21/02 ,  H01L21/223

CPC classification number: H01L21/0234 ,  H01L21/02326 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/2236 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32105

Abstract: Techniques include a plasma oxidation treatment to modify a material to a predetermined thickness around a mandrel or spacer or other structure. This plasma oxidation is then followed by a chemical oxide removal treatment. With only a portion of the structures being oxidized, or by selective masking a portion of oxidized structures, the chemical oxide removal treatment essentially shrinks only a portion of the structures, thereby yielding structures having differing critical dimensions which can function as etch masks to transfer patterns into one or more underlying layers. Accordingly, structures having differing critical dimensions can be fabricated at sub-resolution scales.

Abstract translation: 技术包括等离子体氧化处理以将材料修改成围绕心轴或间隔物或其它结构的预定厚度。 然后进行等离子体氧化，然后进行化学氧化物去除处理。 只有一部分结构被氧化，或者通过选择性掩蔽氧化结构的一部分，化学氧化物去除处理基本上只收缩一部分结构，从而产生具有不同临界尺寸的结构，其可用作蚀刻掩模以转移图案 进入一个或多个下层。 因此，具有不同临界尺寸的结构可以以亚分辨率尺度制造。

公开(公告)号：US11333968B2

公开(公告)日：2022-05-17

申请号：US15902858

申请日：2018-02-22

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Eric Chih-Fang Liu ,  Nihar Mohanty

IPC: H01L21/311 ,  G03F7/00 ,  G03F7/09 ,  G03F1/70 ,  H01L21/033 ,  H01L21/308 ,  H01L21/027

Abstract: An additional non-photoresist layer may be formed on patterned photoresist layers. The additional layer may be preferentially formed on the tops of the photoresist layer versus the sidewalls of the photoresist layer. In addition, the additional layer may be preferential formed on the tops of the photoresist layer versus exposed surfaces of layers underlying the photoresist layer. In this manner, the patterned structures formed by the photoresist layer are less likely to have line opens due to photoresist height variability or the relative thinness of the photoresist height used. Further, the formation of the additional layer may be through a cyclic deposition/trim process. The trim step of the cyclic process may also serve as a descum step that helps reduce line bridging and scumming. In one embodiment, the additional non-photoresist layer may be an organic polymer layer.

公开(公告)号：US20170069510A1

公开(公告)日：2017-03-09

申请号：US15247138

申请日：2016-08-25

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Angelique D. Raley ,  Nihar Mohanty ,  Aelan Mosden

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a second conformal spacer deposition using an oxide, the deposition creating a second conformal layer; performing a second spacer RIE process and a second pull process, wherein generating a second spacer pattern, the second spacer RIE process includes adsorption of N containing gas on a surface of the substrate which activates the surface to react with an F and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

Abstract translation: 提供了一种使用积分方案提高基板上的结构的图案密度的方法，所述方法包括：提供具有第一间隔图案和下层的基板，所述基底层包括第一下层，第二下层， 和目标层; 使用氧化物执行第二共形间隔物沉积，所述沉积产生第二共形层; 执行第二间隔RIE过程和第二拉伸工艺，其中产生第二间隔物图案，第二间隔物RIE方法包括将N含气体吸附在基底表面上，该表面激活表面以与F和/或H反应 的气体形成氟硅酸盐; 并且其中所述集成目标包括在目标间隔物蚀刻速率内选择性地蚀刻间隔膜，增强对第一下层和第二下层的同时选择性并防止图案损伤。

公开(公告)号：US11361993B2

公开(公告)日：2022-06-14

申请号：US16701370

申请日：2019-12-03

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Katie Lutker-Lee

IPC: H01L21/768

Abstract: A process flow is utilized for patterning of dual damascene structures in BEOL process steps. Conductor vias are inversely patterned in the form of pillars that are formed before the final dielectric stack is deposited. The final dielectric stack may include a low-k dielectric and the conductor may be ruthenium. The vias may be formed by forming conductor pillars in patterned voids of a sacrificial layer. After the pillars are formed, certain areas between the pillars can then be backfilled with a dielectric, such as for example, a low-k dielectric material. The trench conductor of the dual damascene structure may then be formed. The sacrificial dielectric may then be removed and an additional layer of low-k dielectric material can then be deposited or coated on the structure to provide the final structure having the dual damascene vias and trenches filled with the conductor surrounded by low-k material.

公开(公告)号：US10580660B2

公开(公告)日：2020-03-03

申请号：US15191963

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

公开(公告)号：US20180323061A1

公开(公告)日：2018-11-08

申请号：US15970168

申请日：2018-05-03

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Sophie Thibaut ,  Richard Farrell

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/0271 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/31144

Abstract: A method to implement self-aligned triple patterning techniques for the processing of substrates is provided. In one embodiment, a self-aligned triple processing technique utilizing an organic spacer is provided. The organic spacer may be formed utilizing any of a wide range of techniques including, but not limited to, plasma deposition and spin on deposition. In one embodiment, the organic spacer may be formed via a cyclic deposition etch process. In one embodiment, the self-aligned triple patterning technique may be utilized to form patterned structures on a substrate at pitches of 26 nm or less.

公开(公告)号：US09786503B2

公开(公告)日：2017-10-10

申请号：US15089961

申请日：2016-04-04

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Nihar Mohanty ,  Akiteru Ko

IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/02186 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.

公开(公告)号：US10971372B2

公开(公告)日：2021-04-06

申请号：US15191956

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.