公开(公告)号：US09960167B1

公开(公告)日：2018-05-01

申请号：US15678132

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin

IPC: H01L27/108 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10897

Abstract: A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the substrate; forming a plurality of openings in the insulating layer and exposing a portion of the memory cells; forming a conductive portion and a metal layer in the openings; removing a portion of the metal layer to form a plurality of first metal portions and a plurality of second metal portions that the first metal portion and the conductive portion form a first connecting structure, and the second metal portion and the conductive portion form a second connecting structure; forming a passivation layer on the first connecting structures; and forming a plurality of first storage nodes and dummy nodes on the substrate and the first storage nodes and the dummy nodes are electrically connected to the second connecting structures and the first connecting structures respectively.

公开(公告)号：US09773887B2

公开(公告)日：2017-09-26

申请号：US14957623

申请日：2015-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Chao-Hung Lin ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Li-Wei Feng ,  Yu-Hsiang Hung

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first spacer around the gate structure, and a contact etch stop layer (CESL) adjacent to the first spacer; forming a cap layer on the gate structure, the first spacer, and the CESL; and removing part of the cap layer for forming a second spacer adjacent to the CESL.

公开(公告)号：US20170271197A1

公开(公告)日：2017-09-21

申请号：US15610574

申请日：2017-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

公开(公告)号：US20170092737A1

公开(公告)日：2017-03-30

申请号：US15378015

申请日：2016-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for manufacturing a nanowire transistor device includes the following steps: A substrate is provided, and the substrate includes a plurality of nanowires suspended thereon. Each of the nanowires includes a first semiconductor core. Next, a first selective epitaxial growth process is performed to form second semiconductor cores respectively surrounding the first semiconductor cores. The second semiconductor cores are spaced apart from the substrate. After forming the second semiconductor core, a gate is formed on the substrate.

公开(公告)号：US09583394B2

公开(公告)日：2017-02-28

申请号：US15293292

申请日：2016-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L21/324 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/308 ,  H01L27/092 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

Abstract translation: 本发明提供一种半导体结构的形成方法，其特征在于，首先，设置具有第一鳍结构和设置在其上的第二鳍结构的衬底，接着，在所述第一鳍结构和所述第二鳍结构之间形成第一隔离区 鳍结构，与第一隔离区相对地形成第二隔离区，并且在第一鳍结构和第二鳍结构的一侧形成至少外延层，其中外延层具有底表面 所述底表面从所述第一鳍结构延伸到所述第二鳍结构，并且所述底表面低于所述第一隔离区域的底表面和所述第二隔离区域的顶表面，此外，所述外延层具有阶梯状 形侧壁轮廓。

公开(公告)号：US20170005102A1

公开(公告)日：2017-01-05

申请号：US14816081

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域，第二区域和第三区域的衬底; 在所述第一区域，所述第二区域和所述第三区域上形成多个间隔物; 形成第一图案化掩模以覆盖第一区域和第二区域上的间隔物; 并移除第三区域上的间隔物。

公开(公告)号：US09484263B1

公开(公告)日：2016-11-01

申请号：US14926003

申请日：2015-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.

Abstract translation: 去除栅极上的硬掩模的方法包括形成第一栅极结构和第二栅极结构。 第一栅极结构包括第一栅极，设置在第一栅极上的第一硬掩模和围绕第一栅极和第一硬掩模的第一隔离物，其中第二栅极结构包括第二栅极，设置在第二栅极上的第二硬掩模 栅极和围绕第二栅极和第二硬掩模的第二隔板。 随后，围绕第一硬掩模的第一间隔物和围绕第二硬掩模的第二间隔物被去除。 之后，形成介电层以覆盖第一硬掩模和第二硬掩模。 最后，去除第二电介质层，第一掩模层和第二掩模层。

公开(公告)号：US20160218179A1

公开(公告)日：2016-07-28

申请号：US14634904

申请日：2015-03-02

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core.

Abstract translation: 纳米线晶体管器件包括衬底，形成在衬底上的多个纳米线和围绕每个纳米线的至少一部分的栅极。 纳米线分别包括第一半导体芯和围绕第一半导体芯的第二半导体芯。 第二半导体芯的晶格常数与第一半导体芯的晶格常数不同。

公开(公告)号：US09349653B2

公开(公告)日：2016-05-24

申请号：US14539225

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Chih-Sen Huang ,  Li-Wei Feng ,  Jyh-Shyang Jenq

IPC: H01L21/8228 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.

Abstract translation: 提供一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成翅片结构和层间电介质层。 在基板上形成多个栅极结构。 在栅极结构上形成盖层。 在盖层上形成硬掩模。 在硬掩模上形成覆盖栅极结构的第一图案化光致抗蚀剂层。 硬掩模被蚀刻和图案化以形成图案化的硬掩模，使得图案化的硬掩模覆盖栅极结构。 在图案化的硬掩模上形成包括对应于鳍结构的多个开口的第二图案化光致抗蚀剂层。 蚀刻覆盖层和层间电介质层以形成暴露鳍结构的一部分的多个第一沟槽。

公开(公告)号：US11508614B2

公开(公告)日：2022-11-22

申请号：US17082034

申请日：2020-10-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tzu-Tsen Liu ,  Tsung-Ying Tsai ,  Chien-Ting Ho

IPC: H01L21/764 ,  H01L21/108 ,  H01L21/02 ,  H01L27/24 ,  H01L27/108

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.