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公开(公告)号：US11877520B2
公开(公告)日：2024-01-16
申请号：US18108003
申请日：2023-02-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
CPC classification number: H10N50/80 , G11C11/161 , H01L27/0207 , H10B61/22
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
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公开(公告)号：US11812669B2
公开(公告)日：2023-11-07
申请号：US17835986
申请日：2022-06-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号：US11778920B2
公开(公告)日：2023-10-03
申请号：US17738001
申请日：2022-05-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
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公开(公告)号：US20230309414A1
公开(公告)日：2023-09-28
申请号：US18202275
申请日：2023-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US11744160B2
公开(公告)日：2023-08-29
申请号：US17064606
申请日：2020-10-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
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Patent Agency Ranking
公开(公告)号：US20230247914A1
公开(公告)日：2023-08-03
申请号：US18132989
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.
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公开(公告)号：US11715499B2
公开(公告)日：2023-08-01
申请号：US17224153
申请日：2021-04-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hung-Yueh Chen , Kun-I Chou , Jing-Yin Jhang , Hui-Lin Wang , Yu-Ping Wang
Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
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48.发明公开公开(公告)号：US20230200256A1
公开(公告)日：2023-06-22
申请号：US18108003
申请日：2023-02-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
CPC classification number: H10N50/80 , G11C11/161 , H01L27/0207 , H10B61/22
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
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公开(公告)号：US20230084241A1
公开(公告)日：2023-03-16
申请号：US17500971
申请日：2021-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.
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公开(公告)号：US11508904B2
公开(公告)日：2022-11-22
申请号：US17308057
申请日：2021-05-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
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