公开(公告)号：US09853215B1

公开(公告)日：2017-12-26

申请号：US15365985

申请日：2016-12-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L45/08

Abstract: A resistance switching memory device is provided, including an insulating layer having a top surface, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode formed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has an upper portion protruding from the top surface of the insulating layer, and the upper portion has round corners at edges.

公开(公告)号：US09853091B2

公开(公告)日：2017-12-26

申请号：US15138436

申请日：2016-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou ,  Ching-Pei Hsieh ,  Chia-Shiung Tsai ,  Shih-Chang Liu

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2418 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.

公开(公告)号：US09847378B2

公开(公告)日：2017-12-19

申请号：US15306125

申请日：2014-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Xia Sheng ,  Yoocharn Jeon ,  Jianhua Yang ,  Hans S. Cho ,  Richard H. Henze

IPC: H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/73 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

公开(公告)号：US09837605B2

公开(公告)日：2017-12-05

申请号：US13969394

申请日：2013-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Pei Hsieh ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

公开(公告)号：US09837472B2

公开(公告)日：2017-12-05

申请号：US15412566

申请日：2017-01-23

Applicant: HGST, Inc.

Inventor： Daniel Robert Shepard

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1683

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

公开(公告)号：US09837148B2

公开(公告)日：2017-12-05

申请号：US15163596

申请日：2016-05-24

Applicant: SK hynix Inc.

Inventor： Kyung-Wan Kim

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/008 ,  G11C2013/0083 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

公开(公告)号：US20170346005A1

公开(公告)日：2017-11-30

申请号：US15165903

申请日：2016-05-26

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Ludovic Goux ,  Andrea Fantini ,  Chao-Yang Chen

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

Abstract: A Resistive Random Access Memory (RRAM) device and a method of its manufacture are disclosed. The RRAM device comprises a lower oxygen affinity bottom electrode, a hygroscopic solid-state dielectric layer, comprising hydroxyl groups, and a higher oxygen affinity top electrode. In some embodiments, the hygroscopic solid-state dielectric layer is a rare-earth metal oxide layer.

公开(公告)号：US20170338410A1

公开(公告)日：2017-11-23

申请号：US15531979

申请日：2015-11-05

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Jun OKUNO

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/10

CPC classification number: H01L45/1293 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/16

Abstract: Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.

公开(公告)号：US20170309682A1

公开(公告)日：2017-10-26

申请号：US15138436

申请日：2016-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou ,  Ching-Pei Hsieh ,  Chia-Shiung Tsai ,  Shih-Chang Liu

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/2463 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2418 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.

公开(公告)号：US09799827B2

公开(公告)日：2017-10-24

申请号：US14880108

申请日：2015-10-09

Applicant: SK hynix Inc.

Inventor： Min-Suk Lee ,  Chang-Hyup Shin

IPC: H01L43/12 ,  G11C13/00 ,  H01L43/08 ,  H01L45/00 ,  H01L43/02 ,  G11C27/00

CPC classification number: H01L43/12 ,  G11C13/0004 ,  G11C27/00 ,  G11C2213/52 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A method of manufacturing an electronic device including a semiconductor memory is provided. The method may include forming a material layer for forming a variable resistance element over a substrate, forming a metal layer over the material layer, forming a mask pattern over the metal layer, forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier, performing a surface treatment on the metal layer pattern, and etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer. An external part of the metal layer pattern may be transformed into a metal compound layer. The metal compound layer may have a low etch rate as an etch barrier.