公开(公告)号：US09570516B2

公开(公告)日：2017-02-14

申请号：US14967025

申请日：2015-12-11

Applicant: HGST, Inc.

Inventor： Daniel Robert Shepard

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1683

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract translation: 一种用于制造3-D交叉点存储器阵列的方法，更具体地说涉及制造具有4F2单元尺寸占空比的相变存储器（PCM）和电阻RAM（ReRAM或RRAM）3-D存储器阵列。 使用有限数量的光刻图案化步骤形成多层存储单元的方法适用于每个单元具有单个或多个存储位的存储器件，例如每个单元或更多个单元具有1至8位的单元。 这些位三维堆叠，并且包括基于相变材料的存储器单元，电阻变化材料，磁场对准，机械开关以及基于其他信息存储技术的其它存储器单元。

公开(公告)号：US09837472B2

公开(公告)日：2017-12-05

申请号：US15412566

申请日：2017-01-23

Applicant: HGST, Inc.

Inventor： Daniel Robert Shepard

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1683

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.