公开(公告)号：US20040202958A1

公开(公告)日：2004-10-14

申请号：US10820994

申请日：2004-04-08

Applicant: MITSUI MINING & SMELTING CO., LTD.

Inventor： Tatsuo Kataoka ,  Yoshikazu Akashi

IPC: G03C001/76

CPC classification number: H01L21/4846 ,  C23C18/1608 ,  C23C18/1844 ,  H01L24/06 ,  H05K3/26 ,  H05K2201/0761 ,  H05K2203/0789

Abstract: A plating-pretreatment solution comprising an organic sulfonic acid, thiourea, fluoroboric acid and hypophosphorous acid and a plating-pretreatment method comprising contacting a film carrier tape in which a wiring pattern is formed on a surface of an insulating film with a plating-pretreatment solution comprising an organic sulfonic acid, thiourea, fluoroboric acid and hypophosphorous acid to remove metals remaining on the insulating film. According to the plating-pretreatment solution and the plating-pretreatment method, metals remaining on the surface of the insulating film exposed by etching are removed, and the occurrence of migration is prevented.

Abstract translation: 包含有机磺酸，硫脲，氟硼酸和次磷酸的电镀预处理溶液和电镀预处理方法，包括使绝缘膜表面上形成布线图案的薄膜载带与电镀预处理溶液 包括有机磺酸，硫脲，氟硼酸和次磷酸，以除去残留在绝缘膜上的金属。 根据电镀预处理溶液和电镀预处理方法，除去通过蚀刻暴露的绝缘膜表面上残留的金属，并且防止迁移的发生。

公开(公告)号：US20040201113A1

公开(公告)日：2004-10-14

申请号：US10836162

申请日：2004-04-29

Inventor： Andrew Michael Cherniski ,  James Kristian Koch

IPC: H01L023/48 ,  H01L023/488

CPC classification number: H01L23/48 ,  H01L23/49562 ,  H01L23/49586 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0256 ,  H05K3/301 ,  H05K3/306 ,  H05K3/3447 ,  H05K2201/0133 ,  H05K2201/0761 ,  H05K2201/10166 ,  H05K2201/10424 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49142 ,  Y10T29/49144 ,  Y10T29/53174 ,  Y10T29/53183 ,  H01L2924/00

Abstract: A method and apparatus to eliminate conductive contamination reliability problems for assembled substrates, such as electrical arcing in power semiconductor leads. One embodiment of the invention involves a method for assembling an electrical component having leads on a substrate having conductive contacts, wherein an elastomer part encapsulates the leads of the electrical component. A second embodiment of the invention involves assembling an electrical component having leads to a substrate having conductive contacts, wherein an elastomer shape cut by a punch die encapsulates the leads of the electrical component. A third embodiment of the invention involves an assembled substrate including an electrical component having leads, and an elastomer surrounding the leads to encapsulate the leads.

公开(公告)号：US20040167047A1

公开(公告)日：2004-08-26

申请号：US10783837

申请日：2004-02-19

Inventor： Norio Ishikawa ,  Yumiko Abe ,  Kiyoto Mori

IPC: C11D001/00

CPC classification number: H05K3/26 ,  C11D3/2075 ,  C11D11/0047 ,  H01L21/02063 ,  H05K2201/0761 ,  H05K2203/122

Abstract: The present invention relates to a cleaning solution capable of removing efficiently at the same time particles and metallic impurities from a substrate surface without corroding metallic materials. The cleaning solution for cleaning substrates of electronic materials comprises an organic acid compound and at least one selected from the group consisting of dispersants and surfactants.

Abstract translation: 本发明涉及能够在不腐蚀金属材料的同时从基材表面高效除去颗粒和金属杂质的清洗溶液。 用于清洁电子材料基材的清洁溶液包括有机酸化合物和选自分散剂和表面活性剂中的至少一种。

公开(公告)号：US20040115405A1

公开(公告)日：2004-06-17

申请号：US10316665

申请日：2002-12-11

Inventor： Yeo Kong Hoo ,  Christopher Vernon Smith

IPC: B32B003/00

CPC classification number: B32B15/08 ,  B32B15/14 ,  B32B15/20 ,  B32B27/308 ,  B32B2250/40 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2307/206 ,  B32B2457/08 ,  H01G2/20 ,  H05K1/0256 ,  H05K1/162 ,  H05K3/027 ,  H05K2201/0761 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2203/162 ,  Y10T29/49156 ,  Y10T428/24917

Abstract: A laminate comprising an insulation layer sandwiched between a pair of electrically conductive layers is prepared for electrical insulation testing by using a laser to remove a strip from at least one of the conductive layers proximate the edge of the laminate to electrically isolate a central, bulk portion of the conductive layer from the edges of the laminate. Conductive material that may be smeared across an edge of the laminate will not therefore provide an electrical short between the portion of the conductive layer surrounded by the slot and the second conductive layer on the opposite side of the insulation layer.

Abstract translation: 通过使用激光从邻近层压体的边缘的至少一个导电层去除条带来制备夹在一对导电层之间的绝缘层的层压板，用于电绝缘测试，以电绝缘中间部分 的导电层。 因此，可能被涂抹在层压体的边缘上的导电材料将不会在由狭缝围绕的导电层的部分与绝缘层的相对侧上的第二导电层之间提供电短路。

公开(公告)号：US06730644B1

公开(公告)日：2004-05-04

申请号：US09550152

申请日：2000-04-17

Applicant: Norio Ishikawa ,  Yumiko Abe ,  Kiyoto Mori

Inventor： Norio Ishikawa ,  Yumiko Abe ,  Kiyoto Mori

IPC: C11D102

CPC classification number: H05K3/26 ,  C11D3/2075 ,  C11D11/0047 ,  H01L21/02063 ,  H05K2201/0761 ,  H05K2203/122

Abstract: The present invention relates to a cleaning solution capable of removing efficiently at the same time particles and metallic impurities from a substrate surface without corroding metallic materials. The cleaning solution for cleaning substrates of electronic materials comprises an organic acid compound and at least one selected from the group consisting of dispersants and surfactants.

Abstract translation: 本发明涉及能够在没有腐蚀金属材料的情况下有效地从基材表面除去颗粒和金属杂质的清洗溶液。用于清洁电子材料的基材的清洁溶液包括有机酸化合物和选自以下的至少一种： 由分散剂和表面活性剂组成的组。

公开(公告)号：US20030066865A1

公开(公告)日：2003-04-10

申请号：US10254750

申请日：2002-09-25

Inventor： Nobuyoshi Tsukaguchi ,  Masami Kimura

IPC: B23K031/02 ,  B23K001/20 ,  B23K005/213 ,  B23K020/24

CPC classification number: H05K3/26 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/064 ,  H05K3/38 ,  H05K2201/0355 ,  H05K2201/0761 ,  H05K2203/0796 ,  H05K2203/1184 ,  H05K2203/121

Abstract: After copper plates 14 are bonded to both sides of a ceramic substrate 10 via a brazing filler metal 12, UV curing alkali peeling type resists 16 are applied on predetermined portions of the surfaces of the copper plates 14 to etch undesired portions of the copper plates 14 to form a metal circuit portion. While the resists 16 are maintained, undesired portions of the brazing filler metal 12 and a reaction product, which is produced by a reaction of the brazing filler metal 12 with the ceramic substrate 10, are removed (or undesired portions of the brazing filler metal 12 and a reaction product, which is produced by a reaction of the brazing filler metal 12 with the ceramic substrate 10, are removed, and the side portion of the metal circuit portion is etched). Thereafter, the resists 16 are peeled off, and an NinullP electroless plating 18 is carried out. Thus, in a method for producing a metal/ceramic bonding circuit board, it is possible to easily control the sectional shape of a metal/ceramic bonding circuit board by a smaller number of steps and at low costs, and it is possible to produce a metal/ceramic bonding circuit board which is more reliable with respect to thermal shock resistance and insulation performance.

Abstract translation: 在铜板14通过钎料12接合到陶瓷基板10的两面之后，将UV固化碱剥离型抗蚀剂16施加到铜板14的表面的预定部分上，以蚀刻铜板14的不期望部分 以形成金属电路部分。 在保护抗蚀剂16的同时，去除钎料填充金属12的不希望的部分和通过钎焊料12与陶瓷基板10的反应而产生的反应产物（或钎焊料12的不期望的部分 并且通过钎焊料12与陶瓷基板10的反应产生的反应产物被除去，金属电路部分的侧部被蚀刻）。 然后，剥离抗蚀剂16，进行Ni-P化学镀层18。 因此，在金属/陶瓷接合电路基板的制造方法中，可以通过较少数量的步骤和低成本容易地控制金属/陶瓷接合电路板的截面形状，并且可以制造 金属/陶瓷接合电路板，其耐热冲击性和绝缘性能更可靠。

公开(公告)号：US20020089634A1

公开(公告)日：2002-07-11

申请号：US10000841

申请日：2001-10-24

Inventor： Yasuhito Aruga ,  Satoshi Yatabe ,  Kogo Endo ,  Norihito Harada

IPC: G02F001/1345

CPC classification number: G02F1/1345 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K1/0256 ,  H05K1/0306 ,  H05K2201/0326 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring substrate is formed of a plurality of metal wirings 14e formed on a substrate 7c. A guard wiring 29 fabricated of an electrically conductive oxide such as ITO is interposed between at least a pair of adjacent ones of a plurality of metal wirings 14e. When voltages V1, V2, V3, and V4 applied to the metal wirings 14e are related to be V1>V2 >V3 >V4, a guard wiring 29 is present between a metal wiring 14e functioning as an anode and a metal wiring 14e functioning as a cathode, and the anode metal wiring 14e is prevented from being corroded.

Abstract translation: 布线基板由形成在基板7c上的多个金属布线14e形成。 由诸如ITO的导电氧化物制造的保护布线29插入在多个金属布线14e中的至少一对相邻的金属布线14e之间。 当施加到金属配线14e的电压V1，V2，V3和V4与V1> V2> V3> V4相关时，保护配线29存在于用作阳极的金属布线14e和作为 阴极和阳极金属布线14e被防止腐蚀。

公开(公告)号：US6063481A

公开(公告)日：2000-05-16

申请号：US36065

申请日：1998-03-06

Applicant: Edward Lee Arrington ,  John Christopher Camp ,  Robert Jeffrey Day ,  Edmond Otto Fey ,  Curtis Michael Gunther ,  Thomas Richard Miller

Inventor： Edward Lee Arrington ,  John Christopher Camp ,  Robert Jeffrey Day ,  Edmond Otto Fey ,  Curtis Michael Gunther ,  Thomas Richard Miller

IPC: H05K3/18 ,  H05K3/26 ,  B32B3/00 ,  B32B15/04

CPC classification number: H05K3/26 ,  H05K3/184 ,  H05K2201/0761 ,  H05K2203/0796 ,  Y10S428/901 ,  Y10T428/12396 ,  Y10T428/12715 ,  Y10T428/12861 ,  Y10T428/12868 ,  Y10T428/24917

Abstract: A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g., with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e.g., with a cyanide submersion). The resultant circuitized substrate includes a circuit pattern on a catalyst layer wherein undesirable portions of the catalyst layer and circuit pattern are completely removed between the circuit features of the circuit pattern so that electrical leakage between the circuit features does not occur.

Abstract translation: 用于去除电路化基板上的不期望的导电材料（例如催化剂材料和渗出的电路材料）的方法以及公开的所得的电路化基板。 这种工艺和结果电路有效地解决了残余催化剂材料和残余催化剂材料下渗出的电路材料的非破坏所引起的电短路问题。 该方法包括以下步骤：a）在其上提供具有电路图案（例如铜）的催化剂层（例如钯和锡） b）预处理催化剂层和电路图案（例如，用氰化物浸渍），以除去在电路图案的电路线之间引起漏电的各部分的不希望的部分; c）氧化催化剂层和电路图案（例如，在高于环境条件的温度下使用亚氯酸盐，高锰酸盐，过氧化氢或空气）; 以及d）去除催化剂层的不期望的部分和电路图案的不希望的部分（例如，氰化物浸没）。 所得到的电路化衬底包括在催化剂层上的电路图案，其中在电路图案的电路特征之间催化剂层和电路图案的不期望部分被完全去除，使得电路特征之间的电泄漏不会发生。

公开(公告)号：US6048465A

公开(公告)日：2000-04-11

申请号：US47765

申请日：1998-03-25

Applicant: Masaharu Shirai

Inventor： Masaharu Shirai

IPC: H05K3/18 ,  H05K3/26 ,  H01B13/00 ,  B44C1/22

CPC classification number: H05K3/26 ,  H05K2201/0761 ,  H05K2203/0796 ,  H05K3/181

Abstract: Short circuiting in printed circuit boards made by processes in which a continuous metal layer applied by electroless deposition is etched to form the conductor pattern is eliminated by subjecting the board to an oxidation treatment after etching but before removal of the etching agent.

Abstract translation: 通过对通过无电沉积施加的连续金属层进行蚀刻以形成导体图案的工艺制造的印刷电路板的短路通过在蚀刻之后但在去除蚀刻剂之前进行氧化处理来消除。

公开(公告)号：US5998739A

公开(公告)日：1999-12-07

申请号：US554427

申请日：1995-11-06

Applicant: Masaharu Shirai

Inventor： Masaharu Shirai

IPC: C23F1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18 ,  H05K3/26 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/26 ,  H05K2201/0761 ,  H05K2203/0796 ,  H05K3/002 ,  H05K3/181 ,  Y10T428/24917

Abstract: Short circuiting in printed circuit boards made by processes in which a continuous metal layer applied by electroless deposition is etched to form the conductor pattern is eliminated by subjecting the board to an oxidation treatment after etching but before removal of the etching agent. A circuit board is thereby formed having an insulating material substrate and a conductor formed thereon.

Abstract translation: 通过对通过无电沉积施加的连续金属层进行蚀刻以形成导体图案的工艺制造的印刷电路板的短路通过在蚀刻之后但在去除蚀刻剂之前进行氧化处理来消除。 由此形成具有绝缘材料基板和形成在其上的导体的电路板。