公开(公告)号：US6075929A

公开(公告)日：2000-06-13

申请号：US658496

申请日：1996-06-05

Applicant: John M. MacLaren

Inventor： John M. MacLaren

IPC: G06F13/36 ,  G06F12/02 ,  G06F12/08 ,  G06F13/40 ,  H01J13/00

CPC classification number: G06F13/4054 ,  G06F12/0215

Abstract: A computer system includes a memory device on the first data bus, a requesting device that initiates a delayed memory read transaction on a second data bus, and a bridge device that delivers the delayed memory read transaction to the first data bus and receives from the first data bus completion data requested in the memory read transaction. The bridge device includes a data storage buffer that stores the completion data, and a buffer management element that automatically requests from the memory device additional data to be placed in the data storage buffer.

Abstract translation: 计算机系统包括第一数据总线上的存储设备，在第二数据总线上启动延迟存储器读取事务的请求设备，以及将延迟的存储器读取事务传送到第一数据总线并从第一数据总线接收的桥接器件 在存储器读取事务中请求的数据总线完成数据。 桥接器件包括存储完成数据的数据存储缓冲器，以及缓冲器管理元件，其自动地从存储器件请求要放置在数据存储缓冲器中的附加数据。

公开(公告)号：US6026369A

公开(公告)日：2000-02-15

申请号：US854225

申请日：1997-05-09

Applicant: Peter George Capek

Inventor： Peter George Capek

IPC: G06F13/00 ,  G06F17/30 ,  G06Q30/02 ,  H01J13/00

CPC classification number: G06Q30/02 ,  G06Q30/0256 ,  G06Q30/0277

Abstract: A method of distributing program material to a number of access providers which have identified themselves as having clients meeting profiles specified in a program material placement request, which is typically from an advertiser. More specifically, summary information is transmitted to a control distribution node from each of the access providers, where the summary information describes customer profile information on the customers using each respective access provider. This summary information is then processed by the control distribution node to allocate the number of copies of program material that may be delivered to the clients or customers by each of the access provider nodes.

Abstract translation: 向多个接入提供商分发节目素材的方法，这些接入提供商已经将自己标识为具有客户端会议通常来自广告主的节目素材放置请求中指定的个人资料。 更具体地，摘要信息从每个接入提供商被传送到控制分发节点，其中摘要信息使用每个相应接入提供商描述客户简档信息。 然后由控制分配节点对该摘要信息进行处理，以分配每个接入提供商节点可以传递给客户端或客户的节目素材的份数。

公开(公告)号：US5907668A

公开(公告)日：1999-05-25

申请号：US681973

申请日：1996-07-30

Applicant: Huang Ing-Kai

Inventor： Huang Ing-Kai

IPC: G06K15/02 ,  H04N1/00 ,  H01J13/00 ,  G06F15/00

CPC classification number: H04N1/00238 ,  G06K15/02 ,  H04N1/00206 ,  H04N1/00236 ,  H04N1/00241 ,  G06K2215/0082

Abstract: A color graphic and texture data transmission and duplication system based on the methods and structures of computer structure, central processing unit, data communication, ink-jet printing, embedded circuit, firmware, dual bus, parallel transmission, ASIC, cell active, pin sharing, to achieve the functions of color scanning, fax transmitting, fax receiving, document duplicating, and data printing.

Abstract translation: 基于计算机结构，中央处理单元，数据通信，喷墨打印，嵌入式电路，固件，双总线，并行传输，ASIC，单元有源，引脚共享的方法和结构的彩色图形和纹理数据传输和复制系统 ，实现彩色扫描，传真发送，传真接收，文件复制和数据打印等功能。

公开(公告)号：US5859990A

公开(公告)日：1999-01-12

申请号：US581494

申请日：1995-12-29

Applicant: Mark A. Yarch

Inventor： Mark A. Yarch

IPC: G06F13/28 ,  H01J13/00 ,  G06F7/64

CPC classification number: G06F13/28

Abstract: The present invention provides an alignment logic circuit transferring segments of data from a first storage device to a second storage device. The segments of data are aligned in the first storage device, in a first and second dimension, according to a first configuration. The segments of data are aligned in the second storage device, in the first and second dimension according to a second configuration. The alignment logic circuit includes a first alignment stage, a second alignment stage, and an alignment control logic controls the first alignment stage such that the first alignment stage outputs data aligned in the first dimension according to the second configuration, and the second alignment stage outputs data aligned in the second dimension according to the second configuration.It is also provided a computer system with a DMA controller with a Memory Write and Invalidate logic circuit. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than a recall with a cacheline size, and the current transfer adders is a multiple of the cacheline size.The present invention also provides a computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access controller (DMA). The DMA performs DMA transactions between the first and second buses. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus. The error handling logic aborts a DMA transfer when the error signal is asserted and the retry signal is deasserted.

Abstract translation: 本发明提供一种将数据段从第一存储设备传送到第二存储设备的对准逻辑电路。 根据第一配置，数据段在第一存储设备中以第一和第二维度对齐。 根据第二配置，数据段在第二存储设备中在第一和第二维度中对准。 对准逻辑电路包括第一对准级，第二对准级，对齐控制逻辑控制第一对准级，使得第一对准级根据第二配置输出在第一维中对齐的数据，第二对准级输出 根据第二配置在第二维中对准数据。 它还提供了具有DMA控制器的计算机系统，其具有存储器写入和无效逻辑电路。 存储器写入和无效逻辑电路在DMA字节数大于使用高速缓存行大小的调用时生成内存写入和无效使能信号，当前传输加法器是缓存线大小的倍数。 本发明还提供了一种计算机系统，包括主处理器，耦合到主处理器的第一总线，耦合到第二总线的第二总线，从属电路以及直接存储器存取控制器（DMA）。 DMA在第一和第二总线之间执行DMA事务。 DMA控制器包括耦合到主机处理器的DMA错误处理逻辑，用于接收指示从属电路的重试请求的重试信号。 DMA错误处理逻辑还接收指示第一总线上的错误的错误信号。 错误处理逻辑在发出错误信号并重试信号被断言时中止DMA传输。

公开(公告)号：US5822548A

公开(公告)日：1998-10-13

申请号：US586040

申请日：1996-01-16

Applicant: Franklyn H. Story ,  Scott E. Harrow ,  Laura E. Simmons

Inventor： Franklyn H. Story ,  Scott E. Harrow ,  Laura E. Simmons

IPC: G06F13/10 ,  H01J13/00

CPC classification number: G06F13/105

Abstract: A universal asynchronous receiver/transmitter (UART) computer programming interface emulates three-wire interface control. A register select circuit is supplied with address signals from a host CPU and has a plurality of register outputs organized into first and second groups. One of these groups of outputs are those which are required for three-wire operation in communications devices; and these outputs are mapped to the appropriate communications devices or registers. The other group of outputs required for three-wire operation, but with no corresponding function in a communications device, are implemented by means of an UART emulator circuit producing a data output which is coupled to an internal data bus, along with the output of the registers for the communications devices.

Abstract translation: 通用异步收发器（UART）计算机编程接口模拟三线接口控制。 寄存器选择电路被提供有来自主机CPU的地址信号，并且具有组织成第一和第二组的多个寄存器输出。 这些输出组之一是通信设备中三线操作所需的输出; 并将这些输出映射到适当的通信设备或寄存器。 在通信设备中三线操作所需的另一组输出，通过UART仿真器电路来实现，该仿真器电路产生耦合到内部数据总线的数据输出，连同输出的 注册通信设备。

公开(公告)号：US5822547A

公开(公告)日：1998-10-13

申请号：US656799

申请日：1996-05-31

Applicant: Shannon C. Boesch ,  Charles L. Haley

Inventor： Shannon C. Boesch ,  Charles L. Haley

IPC: G06F3/00 ,  G06F13/40 ,  H01J13/00

CPC classification number: G06F13/4081

Abstract: A computer system 10, such as a notebook computer, uses a modular bay 12 to receive optional devices 14. Buffer circuits 36 selectively isolate the device 14 in the modular bay from respective buses 34. An SMI handler, or similar executable routine, recognizes events which affect the modular bay 12 (such as insertion or removal of a device 14 from the modular bay 12), and performs the necessary routines to re-enumerate the system so that the device 14 is properly connected to its bus 34 and that the system software is aware of the hardware connected to computer 10.

Abstract translation: 诸如笔记本计算机的计算机系统10使用模块化隔间12来接收可选设备14.缓冲器电路36选择性地将模块化区域中的设备14与相应的总线34隔离.SMI处理程序或类似的可执行例程识别事件 这些影响模块隔间12（例如从模块隔间12插入或移除设备14），并且执行必要的程序来重新列举系统，使得设备14被正确地连接到其总线34，并且系统 软件知道连接到计算机10的硬件。

公开(公告)号：US5815679A

公开(公告)日：1998-09-29

申请号：US681536

申请日：1996-07-23

Applicant: Johny Liu

Inventor： Johny Liu

IPC: G06F1/16 ,  G06F3/00 ,  H01J13/00

CPC classification number: G06F3/002 ,  G06F1/16

Abstract: An interface device is adapted to control computer peripherals by directly executing drivers installed on the computer and respectively corresponding to the computer peripherals without interrupting currently open applications. The interface device includes a housing, a micro-processor located in the housing for generating control signals corresponding to the computer peripherals and transmitting the control signals to the computer to cause the computer to execute the drivers. A key pad device is located on one surface of the housing, including plural buttons which can be selected by the user to control the corresponding computer peripherals.

Abstract translation: 接口设备适于通过直接执行安装在计算机上的驱动器并且分别对应于计算机外围设备来控制计算机外围设备而不中断当前打开的应用程序。 接口装置包括外壳，位于壳体中的微处理器，用于产生对应于计算机外围设备的控制信号，并将控制信号发送到计算机以使计算机执行驱动器。 键盘装置位于壳体的一个表面上，包括可由用户选择以控制相应的计算机外围设备的多个按钮。

公开(公告)号：US5815674A

公开(公告)日：1998-09-29

申请号：US680443

申请日：1996-07-15

Applicant: Paul A. LaBerge

Inventor： Paul A. LaBerge

IPC: G06F13/362 ,  H01J13/00

CPC classification number: G06F13/362

Abstract: A bus controller controls access to a processor bus by arbitrating between bus requests received from a plurality of bus requesters. The bus controller employs a pipelining arbitration mechanism in which a first bus requests from each bus requester is buffered to allow each bus requester to begin producing a second bus request before one of the first bus requests is selected by arbitration. As such, the bus controller performs arbitration between the first bus requests in parallel with the generation of the second bus requests by the bus requesters. The parallel pipelining approach enables the bus controller to base its arbitration decision on plural bus requests from each bus requester. The bus controller can select two bus requests from a first bus requester before selecting any of the bus requests from the other bus requesters.

Abstract translation: 总线控制器通过在从多个总线请求器接收的总线请求之间进行仲裁来控制对处理器总线的访问。 总线控制器采用流水线仲裁机制，其中缓冲来自每个总线请求者的第一总线请求，以允许每个总线请求者在通过仲裁选择第一总线请求之前开始产生第二总线请求。 这样，总线控制器在总线请求者产生第二总线请求之间并行执行第一总线请求之间的仲裁。 并行流水线方法使得总线控制器能够根据来自每个总线请求者的多个总线请求来对其仲裁决定进行设定。 总线控制器可以选择来自第一总线请求者的两个总线请求，然后从其他总线请求者中选择任何总线请求。

公开(公告)号：US5815673A

公开(公告)日：1998-09-29

申请号：US609175

申请日：1996-03-01

Applicant: L. Randall Mote, Jr.

Inventor： L. Randall Mote, Jr.

IPC: G06F13/36 ,  G06F9/46 ,  G06F13/00 ,  G11C8/00 ,  H01J13/00 ,  H04L25/49

CPC classification number: H04L25/4906

Abstract: Customized circuitry implemented on the transmitting end of an interchip communication bus reduces the number of clock cycles required to transmit control packets over the interchip communication bus. The packet transaction protocol is predicated upon the relationship between consecutive command words sent over the interchip bus so that, if consecutive words at a packet boundary contain the same data, this data can be saved as separate command words by the receiving chip within a single clock cycle. This is accomplished through the generation of a synchronization signal whenever a new packet is started. In a preferred embodiment, bit patterns for the first and/or last word of a packet which are found to be statistically more prevalent are intentionally juxtaposed to increase the probability of consecutive command words having the same information.

Abstract translation: 在芯片间通信总线的发送端实现的定制电路减少了通过芯片间通信总线发送控制分组所需的时钟周期数。 分组事务协议基于通过芯片间总线发送的连续命令字之间的关系，使得如果分组边界处的连续字包含相同的数据，则该数据可以在单个时钟内被接收芯片保存为单独的命令字 周期。 这是通过在新分组开始时产生同步信号来实现的。 在优选实施例中，被发现在统计学上更普遍的分组的第一个和/或最后一个字的位模式有意并置，以增加具有相同信息的连续命令字的概率。

公开(公告)号：US5812799A

公开(公告)日：1998-09-22

申请号：US480738

申请日：1995-06-07

Applicant: William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

Inventor： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

IPC: G06F13/42 ,  H01J13/00

CPC classification number: G06F13/4243

Abstract: A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

Abstract translation: 用于高速微处理器和存储器系统的非阻塞负载缓冲器。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。