公开(公告)号：US20100332877A1

公开(公告)日：2010-12-30

申请号：US12495446

申请日：2009-06-30

Applicant: Mark A. Yarch ,  Hang Nguyen ,  Sanjeev Jain ,  Shaun Conrad

Inventor： Mark A. Yarch ,  Hang Nguyen ,  Sanjeev Jain ,  Shaun Conrad

IPC: G06F1/32

CPC classification number: G06F1/3203

Abstract: A system, apparatus, method and article to reduce power consumption are described. The method may include receiving a power management request for a reduced power consumption state from each of a plurality of processors. A power management request for the reduced power consumption state may be sent to a controller to cache data. Each of the plurality of processors may be instructed to enter the reduced power consumption state. An interrupt may be received to return to an active power consumption state. A power management request may be sent to the controller to flush cached data into a memory. Each of the plurality of processors may be instructed to enter the active power consumption state. Other embodiments are described and claimed.

Abstract translation: 描述了降低功耗的系统，装置，方法和制品。 该方法可以包括从多个处理器中的每一个接收针对降低的功耗状态的功率管理请求。 可以将用于降低功耗状态的功率管理请求发送到控制器以高速缓存数据。 可以指示多个处理器中的每一个进入降低的功耗状态。 可以接收中断以返回到有功功耗状态。 电源管理请求可以被发送到控制器以将缓存的数据刷新到存储器中。 可以指示多个处理器中的每一个进入有功功耗状态。 描述和要求保护其他实施例。

公开(公告)号：US08909862B2

公开(公告)日：2014-12-09

申请号：US12495676

申请日：2009-06-30

Applicant: Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

Inventor： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

IPC: G06F12/08 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F2201/82

Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.

Abstract translation: 涉及处理镜像子系统的乱序事务的方法和装置。 第一设备（即来自第二设备的镜像数据）包括在从写入操作到存储器的数据写入之前跟踪故障写入操作的高速缓存。 可以使用寄存器来跟踪高速缓存的状态以响应特殊事务的接收，这可以是已发布的事务或快照。 一旦在寄存器的选择点处记录的所有缓存条目被清空或以其他方式被无效，则第一设备将数据承诺的确认传送到存储器。 设备可以通过外围组件互连快速（PCIe）互连进行通信，并且可以包括点到点或串行链路。 各种组件可以在相同的集成电路管芯上。 不间断的电源或电池可能会供电以响应电源故障。

公开(公告)号：US06848055B1

公开(公告)日：2005-01-25

申请号：US09535474

申请日：2000-03-23

Applicant: Mark A. Yarch

Inventor： Mark A. Yarch

IPC: H01L21/822 ,  G06F1/32 ,  H01L27/04 ,  G06F1/28

CPC classification number: G06F1/3203

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has two voltage domain regions. The integrated circuit provides for changing the operational voltage of one of the voltage domain regions with respect to the other.

Abstract translation: 简而言之，根据本发明的一个实施例，集成电路具有两个电压域区域。 该集成电路用于改变一个电压域区域相对于另一个的工作电压。

公开(公告)号：US6003122A

公开(公告)日：1999-12-14

申请号：US724179

申请日：1996-09-30

Applicant: Mark A. Yarch ,  Byron R. Gillespie

Inventor： Mark A. Yarch ,  Byron R. Gillespie

IPC: G06F13/28 ,  G06F13/00

CPC classification number: G06F13/28

Abstract: An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration.A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size.A computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access (DMA) controller is also provided. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus and a DMA IDLE. The error handling logic aborts a DMA transfer when the error signal and the DMA signal are asserted and the retry signal is deasserted.

Abstract translation: 提供了将数据段从第一存储设备传送到第二存储设备的对准逻辑电路。 对准逻辑电路包括第一和第二对准级，以及对准控制逻辑，其控制第一和第二对准级，使得第一对准级根据第二配置输出在第一维中对齐的数据，并且第二对准级输出 根据第二配置在第二维度中排列数据。 提供具有DMA控制器的计算机系统，其具有存储器写入和无效逻辑电路。 当DMA字节数大于或等于高速缓存行大小时，存储器写入和无效逻辑电路产生存储器写入和无效使能信号，并且当前传输加法器是高速缓存行大小的倍数。 还提供了包括主机处理器，耦合到主处理器的第一总线，耦合到第二总线的第二总线，从属电路和直接存储器存取（DMA）控制器）的计算机系统。 DMA控制器包括耦合到主机处理器的DMA错误处理逻辑，用于接收指示从属电路的重试请求的重试信号。 DMA错误处理逻辑还接收指示第一总线上的错误和DMA IDLE的错误信号。 当错误信号和DMA信号被断言并且重试信号被断言时，错误处理逻辑中止DMA传输。

公开(公告)号：US20100306437A1

公开(公告)日：2010-12-02

申请号：US12471616

申请日：2009-05-26

Applicant: Matthew W. Heath ,  Mohan K. Nair ,  Guadalupe J. Garcia ,  Bibbin Chacko ,  Timothy F. Waite ,  Mark A. Yarch ,  Hang T. Nguyen ,  Saiyid Al-Mahmood ,  Lyonel Renaud ,  Ganesh Kondapuram ,  Richard L. Stout

Inventor： Matthew W. Heath ,  Mohan K. Nair ,  Guadalupe J. Garcia ,  Bibbin Chacko ,  Timothy F. Waite ,  Mark A. Yarch ,  Hang T. Nguyen ,  Saiyid Al-Mahmood ,  Lyonel Renaud ,  Ganesh Kondapuram ,  Richard L. Stout

IPC: G06F13/14

CPC classification number: G06F13/4027 ,  G06F2213/0026

Abstract: A method and apparatus to selectively extend an embedded microprocessor bus through a different external bus are generally presented. In this regard, an apparatus is introduced comprising a first high speed serializer/deserializer (SERDES) bus internal to an integrated circuit device to couple an embedded microprocessor with an embedded component, a second high speed SERDES bus different from the first bus to couple the embedded component with an external interface of the integrated circuit device, and extension circuitry to selectively bypass the embedded component and extend the first bus to function at the external interface over a physical layer of the second bus. Other embodiments are also described and claimed.

Abstract translation: 通常呈现通过不同的外部总线选择性地扩展嵌入式微处理器总线的方法和装置。 在这方面，引入一种装置，其包括集成电路装置内部的第一高速串行器/解串器（SERDES）总线，以将嵌入式微处理器与嵌入式组件耦合，第二高速SERDES总线与第一总线不同以耦合 嵌入式组件与集成电路设备的外部接口，以及扩展电路，用于选择性地旁路嵌入式组件，并且扩展第一总线以在第二总线的物理层上在外部接口处工作。 还描述和要求保护其他实施例。

公开(公告)号：US5859990A

公开(公告)日：1999-01-12

申请号：US581494

申请日：1995-12-29

Applicant: Mark A. Yarch

Inventor： Mark A. Yarch

IPC: G06F13/28 ,  H01J13/00 ,  G06F7/64

CPC classification number: G06F13/28

Abstract: The present invention provides an alignment logic circuit transferring segments of data from a first storage device to a second storage device. The segments of data are aligned in the first storage device, in a first and second dimension, according to a first configuration. The segments of data are aligned in the second storage device, in the first and second dimension according to a second configuration. The alignment logic circuit includes a first alignment stage, a second alignment stage, and an alignment control logic controls the first alignment stage such that the first alignment stage outputs data aligned in the first dimension according to the second configuration, and the second alignment stage outputs data aligned in the second dimension according to the second configuration.It is also provided a computer system with a DMA controller with a Memory Write and Invalidate logic circuit. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than a recall with a cacheline size, and the current transfer adders is a multiple of the cacheline size.The present invention also provides a computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access controller (DMA). The DMA performs DMA transactions between the first and second buses. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus. The error handling logic aborts a DMA transfer when the error signal is asserted and the retry signal is deasserted.

Abstract translation: 本发明提供一种将数据段从第一存储设备传送到第二存储设备的对准逻辑电路。 根据第一配置，数据段在第一存储设备中以第一和第二维度对齐。 根据第二配置，数据段在第二存储设备中在第一和第二维度中对准。 对准逻辑电路包括第一对准级，第二对准级，对齐控制逻辑控制第一对准级，使得第一对准级根据第二配置输出在第一维中对齐的数据，第二对准级输出 根据第二配置在第二维中对准数据。 它还提供了具有DMA控制器的计算机系统，其具有存储器写入和无效逻辑电路。 存储器写入和无效逻辑电路在DMA字节数大于使用高速缓存行大小的调用时生成内存写入和无效使能信号，当前传输加法器是缓存线大小的倍数。 本发明还提供了一种计算机系统，包括主处理器，耦合到主处理器的第一总线，耦合到第二总线的第二总线，从属电路以及直接存储器存取控制器（DMA）。 DMA在第一和第二总线之间执行DMA事务。 DMA控制器包括耦合到主机处理器的DMA错误处理逻辑，用于接收指示从属电路的重试请求的重试信号。 DMA错误处理逻辑还接收指示第一总线上的错误的错误信号。 错误处理逻辑在发出错误信号并重试信号被断言时中止DMA传输。

公开(公告)号：US20100332756A1

公开(公告)日：2010-12-30

申请号：US12495676

申请日：2009-06-30

Applicant: Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

Inventor： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

IPC: G06F12/08 ,  G06F1/30

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F2201/82

Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.

Abstract translation: 描述与处理镜像子系统的乱序事务相关的方法和装置。 在一个实施例中，在将写入操作的数据写入存储器之前，设备（即来自另一个设备的数据镜像）包括高速缓存以跟踪不合格的写入操作。 一旦由寄存器在选择点记录的所有高速缓存条目被清空或以其它方式被无效，则可以使用寄存器来跟踪高速缓存的状态并导致将数据承诺的确认。 还公开了其他实施例。

公开(公告)号：US5761532A

公开(公告)日：1998-06-02

申请号：US581163

申请日：1995-12-29

Applicant: Mark A. Yarch ,  Byron R. Gillespie ,  Marc A. Goldschmidt

Inventor： Mark A. Yarch ,  Byron R. Gillespie ,  Marc A. Goldschmidt

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.

Abstract translation: 提供一种包括本地存储器，耦合到本地存储器的本地总线，外围总线和直接存储器存取（DMA）控制器）的计算机系统。 DMA控制器在本地总线和外设总线之间执行DMA传输数据。 DMA包括用于存储要传送的数据的DMA队列和用于确定DMA控制器的总线所有权状态的总线所有权状态电路。 DMA控制器还包括耦合到DMA队列和状态电路的本地总线接口电路，用于在DMA队列满时通过本地总线暂停数据从本地总线传送到DMA队列而不放弃DMA所有权，并且 状态电路指示DMA控制器拥有外围总线和本地总线的所有权。