公开(公告)号：US20160260442A1

公开(公告)日：2016-09-08

申请号：US14731432

申请日：2015-06-05

Applicant: Faraday Technology Corp.

Inventor： Chung-Chi Hsu

IPC: G10L21/034 ,  G10L21/0264 ,  G10L21/0232 ,  G10L19/02

CPC classification number: G10L25/84 ,  G10L21/0216 ,  G10L21/0232

Abstract: A method and an apparatus for detecting noise of audio signals are provided. The method includes steps of converting an audio signal into a plurality of audio frames, where the audio frames are arranged in chronological order while taking a target frame as a center, calculating a plurality of magnitudes respectively corresponding to a plurality of spectral components of each of the audio frames, calculating differences between the adjacent magnitudes in a time-frequency domain to obtain a plurality of difference values in at least two directions orthogonal to each other in the time-frequency domain, where the time-frequency domain is defined by the audio frames, determining a maximum degree of difference of the magnitudes in the time-frequency domain according to the difference values, and determining whether a part of the audio signal corresponding to the target frame is a noise according to the maximum degree of difference.

Abstract translation: 提供了一种用于检测音频信号噪声的方法和装置。 该方法包括以下步骤：将音频信号转换成多个音频帧，其中音频帧按照时间顺序排列，同时以目标帧为中心，计算分别对应于每个的多个频谱分量的多个量值 音频帧，计算时间 - 频域中的相邻量值之间的差异，以在时间 - 频率域中彼此正交的至少两个方向上获得多个差值，其中时间 - 频域由音频 根据差值确定时频域中的幅度的最大差异度，并且根据最大差异度来确定与目标帧对应的音频信号的一部分是否为噪声。

公开(公告)号：US09275726B2

公开(公告)日：2016-03-01

申请号：US14200040

申请日：2014-03-07

Applicant: Faraday Technology Corp.

Inventor： Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/413

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract translation: 提供静态存储单元。 静态存储单元包括一个数据锁存电路和一个电压提供器。 数据锁存电路被配置为存储位数据。 数据锁存电路具有第一反相器和第二反相器，并且第一反相器和第二反相器彼此耦合。 第一反相器和第二反相器分别接收第一电压和第二电压作为电源电压。 电压提供器向数据锁存电路提供第一电压和第二电压。 当位数据被写入数据锁存电路时，电压提供器根据位数据调节第一和第二电压之一的电压值。

公开(公告)号：US09219897B2

公开(公告)日：2015-12-22

申请号：US14276974

申请日：2014-05-13

Applicant: Faraday Technology Corp.

Inventor： Hung-Chang Chuang

IPC: G06K9/00 ,  H04N9/64 ,  G06T7/40 ,  G06K9/46 ,  G06K9/52

CPC classification number: H04N9/646 ,  G06K9/03 ,  G06K9/4642 ,  G06K9/4652 ,  G06K9/52 ,  G06T5/009 ,  G06T2207/10024 ,  H04N1/58 ,  H04N1/6041 ,  H04N9/67

Abstract: An image sensing apparatus, a color-correction matrix correcting method and a look-up table establishing method are provided. The image sensing apparatus calculates a block statistics value corresponding to a block of pixels in an image sensor array. Based on a look-up table, the image sensing apparatus determines a covariance value corresponding to a current gain value. According to the covariance value and the block statistics value, the image sensing apparatus corrects a color-correction matrix corresponding to the block of pixels. The image sensing apparatus can use an amended color-correction matrix to correct the color of the pixel, so as to reduce chroma noise or other noise.

Abstract translation: 提供了一种图像感测装置，色彩校正矩阵校正方法和查找表建立方法。 图像感测装置计算与图像传感器阵列中的像素块对应的块统计值。 基于查找表，图像感测装置确定与当前增益值对应的协方差值。 根据协方差值和块统计值，图像检测装置校正与像素块对应的颜色校正矩阵。 图像感测装置可以使用修正的颜色校正矩阵来校正像素的颜色，以便降低色度噪声或其他噪声。

公开(公告)号：US20040205264A1

公开(公告)日：2004-10-14

申请号：US10412411

申请日：2003-04-14

Applicant: Faraday Technology Corp.

Inventor： Kuei-yi Chou

IPC: G06F013/28

CPC classification number: G06F13/28

Abstract: A digital signal processor includes a byte direct memory access (DMA) controller and an external memory controller, both of which are coupled to each other. The external memory controller is coupled to a byte memory and other external memories through a common data bus. The byte DMA controller performs a byte DMA operation to the byte memory through the common data bus by controlling the external memory, thereby avoiding an additional data bus. As a result, the digital signal processor according to the present invention has less connecting terminals and achieves a size reduction.

公开(公告)号：US20040098438A1

公开(公告)日：2004-05-20

申请号：US10320458

申请日：2002-12-17

Applicant: Faraday Technology Corp.

Inventor： Jui Chi Chung

IPC: G06F007/38

CPC classification number: G06F17/5045 ,  G06F7/5443 ,  G06F2217/08

Abstract: A multiply accumulator with an optimum timing performs multiplications and additions at the same time by commonly accumulating partial products and addends. First of all, timings of bits of the partial products and timings of bits of the addend are defined. A sum delay parameter and a carry delay parameter associated with adders to be used for constructing the multiply accumulator are retrieved from a circuit design standard cell library. Based on the timings of bits of the partial products and the addend, and the sum delay and carry delay parameters, the bits of the partial products and the addend are assigned to input terminals of the adders, and the input and output terminals of the adders are interconnected by using a three dimensional reduction method. Finally, a net list representative of the multiply accumulator with the optimum timing is output.

Abstract translation: 具有最佳定时的乘法累加器通过共同累积部分乘积和加数来同时执行乘法和加法。 首先，定义了部分乘积的比特和加法比特的定时。 从电路设计标准单元库检索与用于构造乘法累加器的加法器相关联的和延迟参数和进位延迟参数。 基于部分乘积和加数的位的定时以及和延迟和进位延迟参数，将部分乘积和加数的位分配给加法器的输入端，加法器的输入和输出端 通过使用三维还原方法相互连接。 最后，输出表示具有最佳定时的乘法累加器的净列表。

公开(公告)号：US20250157515A1

公开(公告)日：2025-05-15

申请号：US18509318

申请日：2023-11-15

Applicant: Faraday Technology Corp.

Inventor： Sivaramakrishnan Subramanian ,  Hussainvali Shaik ,  Eswar Reddi

IPC: G11C8/18 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

Abstract: A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

公开(公告)号：US20250125806A1

公开(公告)日：2025-04-17

申请号：US18380635

申请日：2023-10-16

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain

IPC: H03L7/08 ,  H03L7/091 ,  H03L7/093

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

公开(公告)号：US12278639B1

公开(公告)日：2025-04-15

申请号：US18380635

申请日：2023-10-16

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain

IPC: H03D3/24 ,  H03L7/08 ,  H03L7/091 ,  H03L7/093

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

公开(公告)号：US12266412B2

公开(公告)日：2025-04-01

申请号：US18323430

申请日：2023-05-25

Applicant: Faraday Technology Corp.

Inventor： Yi-Hsin Tseng ,  Chi-Chang Shuai ,  Yen-Yao Wang

IPC: G11C15/04 ,  G11C29/44 ,  G11C15/00

Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.

公开(公告)号：US20240370204A1

公开(公告)日：2024-11-07

申请号：US18361923

申请日：2023-07-31

Applicant: Faraday Technology Corp.

Inventor： Chang-Chin Chung ,  Shen-Chang Wang

IPC: G06F3/06

Abstract: A command reorder device with a retry function and an operation method thereof are provided. The command reorder device includes a first switch circuit, multiple command buffers, a second switch circuit, and a queue control circuit. The queue control circuit controls the first switch circuit to push an input command of an input command string to a first command buffer. The queue control circuit controls the second switch circuit to pop out an output command from a second command buffer based on a programmable reorder policy. The queue control circuit checks whether an error notification is received during a monitoring period from when the output command is popped out from the second command buffer. According to the check result, the queue control circuit determines either to pop out the output command from the second command buffer again, or to release the memory space of the second command buffer.