公开(公告)号：US12244317B2

公开(公告)日：2025-03-04

申请号：US18351513

申请日：2023-07-13

Applicant: Faraday Technology Corp.

Inventor： Vinod Kumar Jain ,  Mikhail Tamrazyan

IPC: H03K5/24 ,  H03F1/32 ,  H03F3/45

Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.

公开(公告)号：US20250023559A1

公开(公告)日：2025-01-16

申请号：US18351513

申请日：2023-07-13

Applicant: Faraday Technology Corp.

Inventor： Vinod Kumar Jain ,  Mikhail Tamrazyan

IPC: H03K5/24 ,  H03F1/32 ,  H03F3/45

Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.

公开(公告)号：US11949423B2

公开(公告)日：2024-04-02

申请号：US17846018

申请日：2022-06-22

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain ,  Prateek Kumar Goyal

IPC: H03L7/18 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H04L7/00

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H04L7/0016

Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

公开(公告)号：US20230421158A1

公开(公告)日：2023-12-28

申请号：US17846018

申请日：2022-06-22

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain ,  Prateek Kumar Goyal

IPC: H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H04L7/00

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H04L7/0016

Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

公开(公告)号：US20250125806A1

公开(公告)日：2025-04-17

申请号：US18380635

申请日：2023-10-16

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain

IPC: H03L7/08 ,  H03L7/091 ,  H03L7/093

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

公开(公告)号：US12278639B1

公开(公告)日：2025-04-15

申请号：US18380635

申请日：2023-10-16

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain

IPC: H03D3/24 ,  H03L7/08 ,  H03L7/091 ,  H03L7/093

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.