公开(公告)号：US20170186678A1

公开(公告)日：2017-06-29

申请号：US15245605

申请日：2016-08-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： KUO-TING LIN ,  CHIA-WEI CHANG

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/1058 ,  H01L2924/1816 ,  H01L2924/18162

Abstract: A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.

公开(公告)号：US09673178B2

公开(公告)日：2017-06-06

申请号：US14970558

申请日：2015-12-16

Applicant: Powertech Technology Inc.

Inventor： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20170110439A1

公开(公告)日：2017-04-20

申请号：US14970558

申请日：2015-12-16

Applicant: Powertech Technology Inc.

Inventor： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20170084513A1

公开(公告)日：2017-03-23

申请号：US15369802

申请日：2016-12-05

Applicant: Powertech Technology Inc.

Inventor： Shou-Chian Hsu ,  Hiroyuki Fujishima

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/12 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/3511

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

公开(公告)号：US20170047277A1

公开(公告)日：2017-02-16

申请号：US15096293

申请日：2016-04-12

Applicant: Powertech Technology Inc.

Inventor： Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L23/498 ,  H05K3/26 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/5386

Abstract: Provided is a semiconductor structure including a first die and a second die. The first die has a first conductive structure embedded in a dielectric layer. The second die has a second conductive structure embedded in the dielectric layer. A first interface is provided between the first conductive structure and the dielectric layer. A second interface is provided between the second conductive structure and the dielectric layer. A shape of the dielectric layer between the first interface and the second interface is a non-linear shape.

Abstract translation: 提供了包括第一管芯和第二管芯的半导体结构。 第一管芯具有嵌入电介质层中的第一导电结构。 第二管芯具有嵌入电介质层中的第二导电结构。 在第一导电结构和介电层之间提供第一界面。 在第二导电结构和电介质层之间提供第二接口。 第一界面和第二界面之间的介电层的形状是非线性形状。

公开(公告)号：US20160240393A1

公开(公告)日：2016-08-18

申请号：US14623509

申请日：2015-02-17

Applicant: Powertech Technology inc.

Inventor： Hung-Chieh Huang

IPC: H01L21/56 ,  H01L21/66

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L22/12 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: A processing machine of an underfill process comprises a carrier, an automated device, a scanning mechanism, an identifying device and a host. The carrier is suitable for carrying a package substrate provided with chips bonded thereon. The automated device has a dispenser for filling an underfill between each chip and the package substrate. The scanning mechanism is configured on the carrier, and the identifying device is driven by the scanning mechanism to move along a predetermined path over the package substrate and identify positions of the chips before the dispenser fills the underfill between each chip and the package substrate. The identifying device is suitable for outputting an identifying result of chip position, and a movement of the identifying device is independent from a movement of the dispenser. The host receives the identifying result and locates the dispenser of the automated device according to the identifying result.

Abstract translation: 底部填充处理的处理机包括载体，自动化装置，扫描机构，识别装置和主机。 载体适用于承载提供有键合在其上的芯片的封装基板。 自动化装置具有用于在每个芯片和封装基板之间填充底部填充物的分配器。 扫描机构配置在载体上，识别装置由扫描机构驱动，沿着预定路径移动到封装基板上，并在分配器填充每个芯片与封装基板之间的底部填充物之前识别芯片的位置。 识别装置适于输出芯片位置的识别结果，并且识别装置的移动与分配器的运动无关。 主机接收识别结果，并根据识别结果定位自动化设备的分配器。

公开(公告)号：US09412703B1

公开(公告)日：2016-08-09

申请号：US14623517

申请日：2015-02-17

Applicant: Powertech Technology Inc.

Inventor： Chien-Wen Huang ,  Ming-Hung Chang

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection structures between the main substrate and the carrier substrate. The shielding layer covers the top surface and the sidewalls of the molding compound and a portion of the carrier substrate. The shielding layer is electrically grounded through the connection structures.

Abstract translation: 一种芯片封装结构，包括在主衬底和载体衬底之间的主衬底，载体衬底，至少芯片，模塑料，屏蔽层和多个连接结构。 屏蔽层覆盖模制化合物的顶表面和侧壁以及载体基底的一部分。 屏蔽层通过连接结构电接地。

公开(公告)号：US09379043B1

公开(公告)日：2016-06-28

申请号：US14618790

申请日：2015-02-10

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Yi Wang ,  Chao-Shun Chiu ,  Yen-Chu Chen

IPC: H01L21/76 ,  H01L29/49 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/13 ,  H01L29/4991 ,  H01L2221/1047 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least a via reentrant from one surface of the semiconductor body of the chip layer. A plurality of air-gap cavities are formed on the sidewall of the via where the cavities have a depth-to-width ratio not less than one. The dielectric liner covers the sidewall of the via without filling into the air-gap cavities. The conductive filler is disposed in the via without filling into the air-gap cavities due to the isolation of the dielectric liner so as to form an air insulating layer with a plurality of enclosed voids embedded between the semiconductor body and the dielectric liner. Accordingly, RC Delay of the TSV structure can be improved.

Abstract translation: 公开了具有包含芯片层，电介质衬垫和导电填料的具有嵌入空隙的绝缘层的TSV结构。 从芯片层的半导体主体的一个表面至少存在通孔折返。 在通孔的侧壁上形成有多个气隙腔，其中空腔具有不小于1的深度 - 宽度比。 电介质衬垫覆盖通孔的侧壁而不填充到气隙腔中。 导电填料由于绝缘衬垫的隔离而设置在通孔中，而不会填充到气隙腔中，从而形成具有嵌入在半导体本体和电介质衬垫之间的多个封闭空隙的空气绝缘层。 因此，可以提高TSV结构的RC延迟。

公开(公告)号：US12154863B2

公开(公告)日：2024-11-26

申请号：US17454742

申请日：2021-11-12

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/762 ,  H01L23/66 ,  H01Q1/22

Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.

公开(公告)号：US20240347348A1

公开(公告)日：2024-10-17

申请号：US18427834

申请日：2024-01-31

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49827 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistributed circuit structure, a plurality of chips, a second encapsulant, a plurality of supporting members, a first encapsulant, and a plurality of connection terminals is provided. The redistributed circuit structure has a first surface and a second surface opposite to each other. The chips are disposed on the second surface of the redistributed circuit structure. The second encapsulant is disposed on the second surface of the redistributed circuit structure and covers the chips. The supporting members are disposed on the first surface of the redistributed circuit structure. The first encapsulant is disposed on the first surface of the redistributed circuit structure and covers the supporting members. The connection terminals are connected to the supporting members.