公开(公告)号：US20210050249A1

公开(公告)日：2021-02-18

申请号：US16969346

申请日：2019-01-14

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed ,  Rénald Guerin ,  Norbert Colombet

IPC: H01L21/762

Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.

公开(公告)号：US20200336127A1

公开(公告)日：2020-10-22

申请号：US16922758

申请日：2020-07-07

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Isabelle Huyet

IPC: H03H9/02 ,  H01L41/08

Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.

公开(公告)号：US20200321243A1

公开(公告)日：2020-10-08

申请号：US16301276

申请日：2017-05-17

Applicant: SOITEC

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20200228088A1

公开(公告)日：2020-07-16

申请号：US16829604

申请日：2020-03-25

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H01L41/312 ,  H03H3/02 ,  H01L27/20 ,  H01L41/047 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20200186117A1

公开(公告)日：2020-06-11

申请号：US16618696

申请日：2018-06-21

Applicant: Soitec

Inventor： Isabelle Huyet ,  Cedric Charles-Alfred ,  Didier Landru ,  Alexis Drouin

IPC: H03H3/10 ,  H01L41/187 ,  H01L41/312

Abstract: A process for transferring a thin layer consisting of a first material to a support substrate consisting of a second material having a different thermal expansion coefficient, comprises providing a donor substrate composed of an assembly of a thick layer formed of the first material and of a handle substrate having a thermal expansion coefficient similar to that of the support substrate, and the donor substrate having a main face on the side of the thick layer introducing light species into the thick layer to generate a plane of weakness therein and to define the thin layer between the plane of weakness and the main face of the donor substrate; assembling the main face of the donor substrate with a face of the support substrate; and detachment of the thin layer at the plane of weakness, the detachment comprising application of a heat treatment.

公开(公告)号：US20200152459A1

公开(公告)日：2020-05-14

申请号：US16618757

申请日：2018-06-27

Applicant: Soitec

Inventor： Young-Pil Kim

IPC: H01L21/02 ,  C23C16/24 ,  C23C16/26 ,  C23C16/44

Abstract: A process for preparing support comprises the placing of a substrate on a susceptor in a chamber of a deposition system, the susceptor having an exposed surface not covered by the substrate; the flowing of a precursor containing carbon in the chamber at a deposition temperature so as to form at least one layer on an exposed face of the substrate, while at the same time depositing species of carbon and of silicon on the exposed surface of the susceptor. The process also comprises, directly after the removal of the substrate from the chamber, a first etch step consisting of the flowing of an etch gas in the chamber at a first etching temperature not higher than the deposition temperature so as to eliminate at least some of the species of carbon and silicon deposited on the susceptor.

公开(公告)号：US10586783B2

公开(公告)日：2020-03-10

申请号：US15340377

申请日：2016-11-01

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  SOITEC

Inventor： Hubert Moriceau ,  Bruno Imbert ,  Xavier Blot

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/18 ,  H01L21/20 ,  H01L33/00

Abstract: A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.

公开(公告)号：US20200054978A1

公开(公告)日：2020-02-20

申请号：US16341390

申请日：2017-09-21

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk

IPC: B01D46/00

Abstract: A vertical furnace includes a chamber intended for receiving a loading column an inlet channel for fresh gas, arranged at an upper end of the chamber, the loading column comprising an upper portion, and a central portion for supporting a plurality of substrates. The vertical furnace further comprises a trapping device made of at least one material suitable for trapping all or part of the contaminants present in the fresh gas. The trapping device includes a circular part arranged on the upper part of the loading column, the circular part comprising fins regularly distributed over an upper surface of the circular part in order to increase the contact surface of the trapping device with the fresh gas.

公开(公告)号：US20200044140A1

公开(公告)日：2020-02-06

申请号：US16496893

申请日：2018-03-27

Applicant: Soitec

Inventor： Jean-Marc Bethoux ,  Yann Sinquin ,  Damien Radisson

IPC: H01L41/253 ,  H03H3/08 ,  H03H9/02 ,  H01L41/08 ,  H01L41/319

Abstract: A method for adjusting the stress state of a piezoelectric film having a first stress state at room temperature includes a step of forming an assembly including a carrier having a thermal expansion coefficient, a compliant layer placed on the carrier, and the piezoelectric film placed on the compliant layer, the piezoelectric film having a thermal expansion coefficient different from that of the carrier. The method also includes a step of heat treating the assembly, in which the assembly is heated to a treatment temperature above the glass transition temperature of the compliant layer. The present disclosure also relates to a process for fabricating an acoustic wave device comprising the piezoelectric layer the stress state of which was adjusted as described herein.

公开(公告)号：US20190390366A1

公开(公告)日：2019-12-26

申请号：US16481767

申请日：2018-01-31

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Jean-Marc Bethoux

IPC: C30B25/18 ,  C30B29/02 ,  C30B29/66

Abstract: A process for manufacturing a two-dimensional film of a group IV material having a hexagonal crystalline structure, in particular, graphene, comprises formation of a growth substrate, comprising the transfer of a single-crystal metal film suitable for the growth of the two-dimensional film on a support substrate, and epitaxial growth of the two-dimensional film on the metal film of the substrate.