公开(公告)号：US20220095462A1

公开(公告)日：2022-03-24

申请号：US17025939

申请日：2020-09-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wu Chou HSU ,  Hsing Kuo TIEN ,  Chih-Cheng LEE ,  Min-Yao CHEN

IPC: H05K3/30 ,  H01L23/498 ,  H01L23/544 ,  H01L21/48 ,  H05K1/18 ,  H05K1/02

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

公开(公告)号：US20210391284A1

公开(公告)日：2021-12-16

申请号：US16899515

申请日：2020-06-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wu Chou HSU ,  Chih-Cheng LEE ,  Min-Yao CHEN ,  Hsing Kuo TIEN

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.

公开(公告)号：US20210210446A1

公开(公告)日：2021-07-08

申请号：US16735002

申请日：2020-01-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/00

Abstract: A semiconductor device package includes a redistribution structure and an electrical connection. The redistribution structure has an electrical terminal adjacent to a surface of the redistribution structure and a seed layer covering a side surface of the electrical terminal. The electrical connection is disposed on a first surface of the electrical terminal. The seed layer extends to the first surface of the electrical terminal.

公开(公告)号：US20200258826A1

公开(公告)日：2020-08-13

申请号：US16859676

申请日：2020-04-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Li-Chuan TSAI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/16 ,  H01L21/683

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

公开(公告)号：US20190148297A1

公开(公告)日：2019-05-16

申请号：US15815351

申请日：2017-11-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chung Chieh CHANG ,  Ya Fang CHAN ,  Chih-Cheng LEE

IPC: H01L23/535 ,  H01L21/02

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another. The second central axes of the first and second conductive elements are substantially co-linear in the second direction. The second central axis of the third conductive element is substantially parallel to and misaligned from the second central axes of the first and second conductive elements. The first chamfer and the second chamfer are separated by at least one of the first central axis and the second central axis of the first conductive element and are substantially asymmetric.

公开(公告)号：US20180254240A1

公开(公告)日：2018-09-06

申请号：US15450598

申请日：2017-03-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

公开(公告)号：US20180033719A1

公开(公告)日：2018-02-01

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K3/36 ,  H05K3/22 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

公开(公告)号：US20170229402A1

公开(公告)日：2017-08-10

申请号：US15495282

申请日：2017-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Chih-Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/544 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/3512

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

公开(公告)号：US20160315041A1

公开(公告)日：2016-10-27

申请号：US14696355

申请日：2015-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Chih-Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/73204

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract translation: 插入器基板包括嵌入电介质层的第一表面的第一电路图案和嵌入电介质层的第二表面的第二电路图案; 在所述第一电路图案和所述第二电路图案之间的介电层中的中间图案化导电层; 第一导电通孔，其中每个第一导电通孔包括与第一电路图案相邻的第一端和与中间图案化导电层相邻的第二端，其中第一端的宽度大于第二端的宽度; 第二导电通孔，其中每个第二导电通孔包括与第二电路图案相邻的第三端和与中间图案化导电层相邻的第四端，其中第三端的宽度大于第四端的宽度。

公开(公告)号：US20160143149A1

公开(公告)日：2016-05-19

申请号：US14548118

申请日：2014-11-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang SU ,  Chih-Cheng LEE ,  Cheng-Lin HO

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/18 ,  H05K3/46 ,  H05K3/10 ,  H01L23/498 ,  H05K3/30

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

Abstract translation: 公开了半导体封装结构和制造方法。 半导体封装结构包括第一电介质层，第二电介质层，部件，图案化导电层和至少两个导电通孔。 第一电介质层具有与第一表面相对的第一表面和第二表面。 第二电介质层具有与第一表面相对的第一表面和第二表面。 第一电介质层的第二表面附着到第二电介质层的第一表面。 第二电介质层内的部件具有与第一电介质层的第二表面相邻的至少两个电触点。 第一介电层内的图案化导电层与第一介电层的第一表面相邻。 导电通孔穿透第一电介质层并将电触点与图案化的导电层电连接。