公开(公告)号：US20150121520A1

公开(公告)日：2015-04-30

申请号：US14529278

申请日：2014-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Denis Rystsov ,  Sebastien Nussbaum

IPC: G06F21/57 ,  G06F1/26 ,  G06F21/50

CPC classification number: G06F21/57 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/50 ,  G06F21/81 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/171

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

Abstract translation: 本公开提供了用于控制处理器的一个或多个处理核心的功率状态（其可以包括C状态）的方法和装置。 在一方面，提出了一种确保处理器的电源状态改变的示例性方法，所述方法包括以下步骤：从处理器接收电力状态改变请求，所述处理器具有多个潜在功率状态，每个包括工作功率分布 ; 确定与所述处理器相关联的功率状态改变请求模式; 将所述电力状态改变请求转发到所述电力状态改变请求模式是一次性请求模式的安全处理器; 响应于该请求从安全处理器接收电力状态改变请求响应; 以及将所述处理器的当前功率状态调整到所述电力状态改变请求响应包括电力状态改变许可的所述目标电力状态。

公开(公告)号：US20150120978A1

公开(公告)日：2015-04-30

申请号：US14523705

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Liang Chen ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

IPC: G06F12/10 ,  G06F13/24 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F12/1045 ,  G06F12/12 ,  G06F2212/684

Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

Abstract translation: 本发明通过新的原子测试[0]和OR和Mask来提供在硬件中的页表访问和脏位管理。 本发明还提供了一种使ACE能够进行CCI翻译的垫圈。 该垫片进一步提供了ACE和CCI之间的请求转换，针对受害者和探针冲突的死锁避免，ARM屏障处理和电源管理交互。 本发明还提供了一种用于ARM受害者/探测器碰撞处理的解决方案，其使统一的北桥陷入僵局。 这些解决方案包括一个专用的回写虚拟通道，使用4跳协议的IO请求的探测器和MCT中的WrBack重新排序能力，其中受害者通过数据通过请求时更新旧的请求。

公开(公告)号：US20140229678A1

公开(公告)日：2014-08-14

申请号：US14258289

申请日：2014-04-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Lepak ,  Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Benjamin Tsien ,  Greggory D. Donley

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0822 ,  G06F12/0833 ,  Y02D10/13

Abstract: A method and apparatus for accelerated shared data migration between cores, Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.

Abstract translation: 一种用于在内核之间加速共享数据迁移的方法和装置，使用始终迁移协议，当迁移探测器以修改或拥有状态访问目录条目时，该条目将转换为所有状态，并且发送源完成命令而不发送源完成命令 将缓存块所有权或状态信息发送到目录。

公开(公告)号：US20250004652A1

公开(公告)日：2025-01-02

申请号：US18345927

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Guhan Krishnan

IPC: G06F3/06 ,  G06F12/0802

Abstract: The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12135601B2

公开(公告)日：2024-11-05

申请号：US17390271

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Dilip Jha ,  James R. Magro ,  MingLiang Lin ,  Kostantinos Danny Christidis ,  Hui Zhou

IPC: G06F1/00 ,  G06F1/3228 ,  G06F1/3296

Abstract: A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

公开(公告)号：US12111716B2

公开(公告)日：2024-10-08

申请号：US18304849

申请日：2023-04-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3287 ,  G06F1/3265 ,  G06F1/3278 ,  G06F1/3296

Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

公开(公告)号：US12093689B2

公开(公告)日：2024-09-17

申请号：US17032301

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  John Petry ,  Chen-Ping Yang ,  Rostyslav Kyrychynskyi ,  Vydhyanathan Kalyanasundharam

IPC: G06F11/14 ,  G06F1/30 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/46 ,  G06F13/40

CPC classification number: G06F9/3005 ,  G06F9/3877 ,  G06F9/4418 ,  G06F9/463 ,  G06F13/4022

Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.

公开(公告)号：US12086009B2

公开(公告)日：2024-09-10

申请号：US17710521

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  Indrani Paul ,  Benjamin Tsien ,  Stephen V. Kosonocky ,  John P. Petry ,  Christopher T. Weaver

IPC: G06F1/32 ,  G06F1/3234

CPC classification number: G06F1/3234

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

公开(公告)号：US20240219988A1

公开(公告)日：2024-07-04

申请号：US18336541

申请日：2023-06-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Nicholas Carmine DeFiore ,  Sridhar Varadharajulu Gada ,  Benjamin Tsien ,  YanFeng Wang ,  Steven Zhou ,  Duanduan Chen ,  Malcolm Earl Stevens

IPC: G06F1/3209

CPC classification number: G06F1/3209

Abstract: The disclosed device for power management of chiplet interconnects includes multiple chiplets connected via multiple interconnects. The device also includes a control circuit that detects activity states of the chiplets and manages power states of the interconnects based on the detected activity states. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20230341922A1

公开(公告)日：2023-10-26

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.