公开(公告)号：US20240170351A1

公开(公告)日：2024-05-23

申请号：US17992010

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/167 ,  H01L23/49833 ,  H01L23/5385 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Architectures and processes for redistribution layers in a dielectric cavity to enable an embedded component in semiconductor packaging. The architectures pattern redistribution layers (RDL) over a thick seed and remove dielectric material from the RDL conductive contacts to create the dielectric cavity. The architectures enable 2-sided connections for embedded components in the dielectric cavity with minimal disruption to existing process infrastructure. Such an approach can be used not only for integration of photonic devices, but also for any semiconductor packaging requiring dual sided connection within a dielectric cavity.

公开(公告)号：US20240113087A1

公开(公告)日：2024-04-04

申请号：US17957403

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Gang Duan ,  Srinivas Pietambaram ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Debendra Mallik ,  Ravindranath Mahajan ,  Rahul Manepalli

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16235 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1094

Abstract: An apparatus is provided which comprises: an interposer comprising glass, one or more redistribution layers on a first interposer surface, one or more conductive contacts on a second interposer surface opposite the first interposer surface, one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the redistribution layers on the first interposer surface, an integrated circuit device embedded within a cavity in the interposer between the first and second interposer surfaces, the embedded integrated circuit device coupled with a first redistribution layers surface, a stack of two or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface, and mold material surrounding at least one side of the stack of two or more integrated circuit devices. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240112973A1

公开(公告)日：2024-04-04

申请号：US17958053

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49827

Abstract: Through-glass vias (TGVs) are formed without the use of a planarization step to planarize the TGV fill material after filling holes that extend through a glass layer with the fill material. After the holes are filled with the fill material, the fill material is etched and the glass layer is etched. After etching of the glass is performed, the top and bottom surfaces of the glass layer are recessed relative to the top and bottom surfaces of the fill material in the holes, resulting in formation of fill material stubs. TGV pads are then formed on the fill material stubs. The resulting pads can have protrusions that extend away from a surface of the glass layer. If the TGVs are plated through-holes, a portion of the metal lining the inner wall of a TGV hole can extend past a surface of the glass layer and into a TGV pad.

公开(公告)号：US11929212B2

公开(公告)日：2024-03-12

申请号：US16392028

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Gang Duan ,  Srinivas Pietambaram ,  Kristof Darmawikarta

IPC: H01G4/33 ,  H01G4/224 ,  H01G4/30 ,  H01G4/38 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01G4/12

CPC classification number: H01G4/33 ,  H01G4/224 ,  H01G4/306 ,  H01G4/38 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16 ,  H01G4/1227 ,  H01L2224/16227

Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.

公开(公告)号：US20240079334A1

公开(公告)日：2024-03-07

申请号：US17903856

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: A microelectronic structure, a semiconductor package including the structure, an IC device assembly including the structure, and a method of making the structure. The microelectronic structure includes: a first buildup layer and a second buildup layer including respective first and second electrically conductive structures; and a bridge layer including a glass material extending across a width thereof, the bridge layer between the first buildup layer and the second buildup layer and comprising: an interconnect bridge including third electrically conductive structures coupling a first set of the first electrically conductive structures to a second set of the first electrically conductive structures. Through glass vias (TGVs) extending from a top surface to a bottom surface of the bridge layer, the TGVs coupling a third set of the first electrically conductive structures to at least some of the second electrically conductive structures.

公开(公告)号：US11923307B2

公开(公告)日：2024-03-05

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US11622448B2

公开(公告)日：2023-04-04

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Srinivas Pietambaram ,  Andrew J. Brown ,  Gang Duan ,  Jeremy Ecton ,  Sheng C. Li

IPC: H05K1/11 ,  H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

公开(公告)号：US20230078395A1

公开(公告)日：2023-03-16

申请号：US17472048

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Robin Mcree ,  Yosuke Kanaoka ,  Gang Duan ,  Jinhe Liu ,  Timothy A. Gosselin

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed herein are embedded heterogeneous architectures having minimized die shift and methods for manufacturing the same. The architectures may include a substrate, a bridge, and a material attached to the substrate. The substrate may include a first subset of vias and a second subset of vias. The bridge may be located in between the first subset and the second subset of vias. The material may include a first portion located proximate the first subset of vias, and a second portion located proximate the second subset of vias. The first and second portions may define a partial boundary of a cavity formed within the substrate and the bridge may be located within the cavity.

公开(公告)号：US20230078099A1

公开(公告)日：2023-03-16

申请号：US17473414

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Gang Duan ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bai Nie

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L21/48

Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.