公开(公告)号：US10658281B2

公开(公告)日：2020-05-19

申请号：US15721321

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20190103348A1

公开(公告)日：2019-04-04

申请号：US15721321

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20250006671A1

公开(公告)日：2025-01-02

申请号：US18217123

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Marcel Arlan Wall ,  Hamid Azimi ,  Rahul N. Manepalli ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Steve Cho ,  Thomas L. Sounart ,  Gang Duan ,  Jung Kyu Han ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01L23/00

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US20200211952A1

公开(公告)日：2020-07-02

申请号：US16814215

申请日：2020-03-10

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20240006299A1

公开(公告)日：2024-01-04

申请号：US17855568

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jason Steill ,  Yi Yang ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Marcel Arlan Wall ,  Gang Duan ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/49822 ,  H01L21/4857

Abstract: Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same. The microelectronics packages may include a core material, a first plurality of pads, and a silicon nitride layer. The first plurality of pads are attached to the core material. The silicon nitride layer is attached to the core material. The silicon nitride material defines respective openings to expose at least a portion of each of the first plurality of pads.