公开(公告)号：US10860682B2

公开(公告)日：2020-12-08

申请号：US16839013

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Phil Knag ,  Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G06F17/16 ,  G11C11/419 ,  G11C11/418 ,  G11C7/12 ,  G11C8/08 ,  G06G7/16 ,  G06G7/22 ,  G11C11/56 ,  G06F9/30 ,  G11C7/10 ,  G06N3/063

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

公开(公告)号：US20200286686A1

公开(公告)日：2020-09-10

申请号：US16296082

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US20200279805A1

公开(公告)日：2020-09-03

申请号：US16647691

申请日：2017-11-03

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Jasmeet S. Chawla ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young ,  Robert L. Bristol

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/22 ,  H01L21/768 ,  H01L43/02 ,  H01F10/32

Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.

公开(公告)号：US20200162024A1

公开(公告)日：2020-05-21

申请号：US16192841

申请日：2018-11-16

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Raseong Kim ,  Sasikanth Manipatruni ,  Ian A. Young ,  Gary Alfred Allen ,  Tanay Gosavi

IPC: H03B5/24 ,  H01L29/78 ,  H01L27/06

Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.

公开(公告)号：US20200160145A1

公开(公告)日：2020-05-21

申请号：US16194792

申请日：2018-11-19

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Ian A. Young

IPC: G06N3/04 ,  G06N3/08

Abstract: Embodiments may relate to a system to be used in an oscillating neural network (ONN). The system may include a control node and a plurality of nodes wirelessly communicatively coupled with a control node. A node of the plurality of nodes may be configured to identify an oscillation frequency of the node based on a weight W and an input X. The node may further be configured to transmit a wireless signal to the control node, wherein a frequency of the wireless signal oscillates based on the identified oscillation frequency. Other embodiments may be described or claimed.

公开(公告)号：US10608167B2

公开(公告)日：2020-03-31

申请号：US15751102

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18 ,  H01L43/06

Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.

公开(公告)号：US20190386662A1

公开(公告)日：2019-12-19

申请号：US16009110

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian A. Young ,  Benjamin Buford ,  Tanay Gosavi ,  Kaan Oguz ,  John J. Plombon

IPC: H03K19/18 ,  H01L43/06 ,  H03K19/0944 ,  H01F10/32 ,  H01F41/30

Abstract: An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.

公开(公告)号：US20190386208A1

公开(公告)日：2019-12-19

申请号：US16009035

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Benjamin Buford ,  Kaan Oguz ,  John J. Plombon ,  Ian A. Young

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/02

Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.

公开(公告)号：US10320404B2

公开(公告)日：2019-06-11

申请号：US15300266

申请日：2014-06-18

Applicant: Intel Corporation

Inventor： Sasikanth Sasi Manipatruni ,  George I. Bourianoff ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03L7/26 ,  B82Y25/00 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32 ,  H01L43/06 ,  H01L43/08 ,  H03B15/00

Abstract: Described is an oscillating apparatus which comprises: an interconnect with spin-coupling material (e.g., Spin Hall Effect (SHE) material); and a magnetic stack having two magnetic layers such that one of the magnetic layers is coupled to the interconnect, wherein each of the two magnetic layers have respective magnetization directions to cause the magnetic stack to oscillate.

公开(公告)号：US20190007033A1

公开(公告)日：2019-01-03

申请号：US15992080

申请日：2018-05-29

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H03K3/356 ,  H03K3/3562 ,  H01L29/66 ,  H03K3/012

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.