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    System, apparatus and method for fine-grain address space selection in a processor
    51.
    发明授权
    System, apparatus and method for fine-grain address space selection in a processor 有权

    公开(公告)号：US11461099B2

    公开(公告)日：2022-10-04

    申请号：US16911441

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Gilbert Neiger ,  Philip Lantz ,  Sanjay K. Kumar

    IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

    Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

    SECURE ADDRESS TRANSLATION SERVICES USING A PERMISSION TABLE
    52.
    发明申请
    SECURE ADDRESS TRANSLATION SERVICES USING A PERMISSION TABLE 有权

    公开(公告)号：US20220309008A1

    公开(公告)日：2022-09-29

    申请号：US17842094

    申请日：2022-06-16

    Applicant: Intel Corporation

    Inventor： David Koufaty ,  Rajesh Sankaran ,  Anna Trikalinou ,  Rupin Vakharwala

    IPC: G06F12/14 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/42

    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes memory for storage of data, an IOMMU coupled to the memory, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the memory, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the memory pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.

    Address space identifier management in complex input/output virtualization environments
    53.
    发明授权
    Address space identifier management in complex input/output virtualization environments 有权

    公开(公告)号：US11269782B2

    公开(公告)日：2022-03-08

    申请号：US16772765

    申请日：2018-03-28

    Applicant: INTEL CORPORATION

    Inventor： Kun Tian ,  Xiao Zheng ,  Ashok Raj ,  Sanjay Kumar ,  Rajesh Sankaran

    IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

    Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

    Posted interrupt processing in virtual machine monitor
    54.
    发明授权
    Posted interrupt processing in virtual machine monitor 有权

    公开(公告)号：US11080088B2

    公开(公告)日：2021-08-03

    申请号：US16226367

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Arumugam Thiyagarajah ,  Rajesh Sankaran ,  Dharmendra Thakkar

    IPC: G06F9/48 ,  G06F9/455 ,  G06F9/54

    Abstract: A processor includes a processor core, a processor cache to store reporting data structures including a queue structure, and an interrupt posting circuit coupled to the processor core and the processing cache. The interrupt posting circuit receives an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core. The VM is managed by a virtual machine monitor (VMM) executed by the processor core. The interrupt posting circuit determines the VP is in an inactive state and records the interrupt request in a first posted data structure allocated by the VMM for the VP in main memory coupled to the processor. The interrupt posting circuit updates location information stored in the reporting data structures based on recording the interrupt request in the first posted data structure to generate updated location information that identifies a location of the interrupt request.

    Techniques to provide cache coherency based on cache type
    55.
    发明授权
    Techniques to provide cache coherency based on cache type 有权

    公开(公告)号：US11016894B2

    公开(公告)日：2021-05-25

    申请号：US15670171

    申请日：2017-08-07

    Applicant: INTEL CORPORATION

    Inventor： Rajesh Sankaran ,  Ishwar Agarwal ,  Stephen Van Doren

    IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0817

    Abstract: Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.

    VIRTUALIZING INTERRUPT PRIORITIZATION AND DELIVERY
    56.
    发明申请
    VIRTUALIZING INTERRUPT PRIORITIZATION AND DELIVERY 审中-公开

    公开(公告)号：US20200341921A1

    公开(公告)日：2020-10-29

    申请号：US15931868

    申请日：2020-05-14

    Applicant: Intel Corporation

    Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Gideon Gerzon ,  Richard Uhlig ,  Sergiu Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

    IPC: G06F13/26 ,  G06F13/24 ,  G06F9/30 ,  G06F9/455

    Abstract: Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

    Shared accelerator memory systems and methods
    57.
    发明授权
    Shared accelerator memory systems and methods 有权

    公开(公告)号：US10817441B2

    公开(公告)日：2020-10-27

    申请号：US16370587

    申请日：2019-03-29

    Applicant: INTEL CORPORATION

    Inventor： Sanjay Kumar ,  David Koufaty ,  Philip Lantz ,  Pratik Marolia ,  Rajesh Sankaran ,  Koen Koning

    IPC: G06F13/16 ,  G06F12/1027 ,  G06F3/06

    Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes virtual-to-physical address translation circuitry and migration circuitry. The virtual-to-physical address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits. Thus, the processor memory circuitry and accelerator memory circuitry may be dynamically allocated to advantageously minimize system latency attributable to data access operations.

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