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公开(公告)号：US20150257101A1
公开(公告)日：2015-09-10
申请号：US14595085
申请日：2015-01-12
Applicant: Intel Corporation
Inventor： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
CPC classification number: H04W52/0225 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3296 , G06F13/4282 , H04L43/0858 , Y02D10/151 , Y02D70/00 , Y02D70/142 , Y02D70/23
Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
Abstract translation: 对于一个公开的实施例，可以识别对于下游设备的至少一部分从第一状态到第二不同状态的转变。 第一和第二状态可以对应于与下游设备的至少一部分的活动有关的不同级别。 响应于所识别的一个或多个上游设备的转换，至少部分地基于服务等待时间来对应于服务等待时间的数据可被发送到上游设备以管理电力。 还公开了其他实施例。
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公开(公告)号：US20150205344A1
公开(公告)日：2015-07-23
申请号：US14129950
申请日：2013-06-28
Applicant: INTEL CORPORATION
Inventor： Paul S. Diefenbaugh , Eugene Gorbatov , Andrew Henroid , Eric C. Samson , Barnes Cooper
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3246 , G06F1/3287 , G06F9/4893 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。
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公开(公告)号：US08874947B2
公开(公告)日：2014-10-28
申请号：US13893846
申请日：2013-05-14
Applicant: Intel Corporation
Inventor： Efraim Rotem , Barnes Cooper , Guy Therien , Eliezer Weissmann , Anil Aggarwal
CPC classification number: G06F1/3206 , G06F1/3203 , G06F1/3243 , Y02D10/152
Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
Abstract translation: 提出了处理平台和处理平台中央处理单元功耗控制方法。 通过操作该方法，处理平台能够设置较高的性能状态限制和较低的性能状态限制。 较高的性能状态限制基于中央处理单元活动速率值，较低的性能状态限制基于操作系统执行操作系统任务的最低要求。 性能状态值根据电源管理策略在下限和上限的范围内变化。
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公开(公告)号：US20220262427A1
公开(公告)日：2022-08-18
申请号：US17178015
申请日：2021-02-17
Applicant: Intel Corporation
Inventor： Nivedha Krishnakumar , Virendra Vikramsinh Adsure , Jaya Jeyaseelan , Nadav Bonen , Barnes Cooper , Toby Opferman , Vijay Bahirji , Chia-Hung Kuo
IPC: G11C11/406 , G11C5/14 , G11C11/4074 , G11C11/402
Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.
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公开(公告)号：US20200334264A1
公开(公告)日：2020-10-22
申请号：US16914175
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： William J. Lewis , Barnes Cooper , Aleksander Magi , Marko Bartscherer
IPC: G06F16/2457 , G06K9/62 , H04L29/08
Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include one or more processors, a user proximity sensor, a user proximity engine, and a state synchronization engine. The user proximity engine is configured to cause the one or more processors to determine if the electronic device is the most relevant device to the user. The state synchronization engine configured to cause the one or more processors to determine the state of the electronic device and communicate the state of the electronic device to a second electronic device if the electronic device is determined to be the most relevant device to the user.
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Patent Agency Ranking
56.发明授权公开(公告)号：US10678199B2
公开(公告)日：2020-06-09
申请号：US15191123
申请日：2016-06-23
Applicant: INTEL CORPORATION
Inventor： Barnes Cooper , Neil W. Songer
IPC: G06F1/32 , G05B15/02 , G06F1/3228 , G06F1/3296 , G06F9/46 , G06F1/20 , G06F11/30 , G06F1/3234
Abstract: Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.
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公开(公告)号：US10481661B2
公开(公告)日：2019-11-19
申请号：US15086007
申请日：2016-03-30
Applicant: INTEL CORPORATION
Inventor： Barnes Cooper , Vidoot Ponnala Rathnakar
Abstract: A system to provide an indication to a power supply unit that a computing device operably coupled to the power supply unit is idle. The system includes an interface including power rails to provide power from the power supply unit to the computing device and an idle control line to provide an indication from the computing device to the power supply unit that the computing device is idle.
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公开(公告)号：US20190278339A1
公开(公告)日：2019-09-12
申请号：US16421217
申请日：2019-05-23
Applicant: Intel Corporation
Inventor： Barnes Cooper , Aleksander Magi , Arvind Kumar , Giuseppe Raffa , Wendy March , Marko Bartscherer , Irina Lazutkina , Duck Young Kong , Meng Shi , Vivek Paranjape , Vinod Gomathi Nayagam , Glen J. Anderson
Abstract: Methods and apparatus to operate closed-lid portable computers are disclosed. An example apparatus includes a camera input analyzer to analyze image data captured by a world facing camera on a portable computer when a lid of the portable computer is in a closed position. The world facing camera is on a first side of the lid. The portable computer includes a primary display on a second side of the lid opposite the first side. The example apparatus further includes a secondary display controller to render content via a secondary display of the portable computer in response to the analysis of the image data. The secondary display controller is to render the content on the secondary display while the lid of the portable computer is in the closed position and the primary display is turned off.
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公开(公告)号：US10345889B2
公开(公告)日：2019-07-09
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
IPC: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/07
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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公开(公告)号：US10182398B2
公开(公告)日：2019-01-15
申请号：US15453208
申请日：2017-03-08
Applicant: Intel Corporation
Inventor： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.
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