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    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
    52.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION 有权

    公开(公告)号：US20210328589A1

    公开(公告)日：2021-10-21

    申请号：US17359466

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Programmable logic device with fine-grained disaggregation
    53.
    发明授权
    Programmable logic device with fine-grained disaggregation 有权

    公开(公告)号：US11070209B2

    公开(公告)日：2021-07-20

    申请号：US16788760

    申请日：2020-02-12

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Interface bus for inter-die communication in a multi-chip package over high density interconnects
    54.
    发明授权
    Interface bus for inter-die communication in a multi-chip package over high density interconnects 有权

    公开(公告)号：US11056452B2

    公开(公告)日：2021-07-06

    申请号：US16023724

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Md Altaf Hossain

    IPC: H01L25/065 ,  G06F13/42 ,  H01L23/00 ,  G06F13/38 ,  G06F13/14

    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.

    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
    55.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION 审中-公开

    公开(公告)号：US20200083890A1

    公开(公告)日：2020-03-12

    申请号：US16123765

    申请日：2018-09-06

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC: H03K19/177 ,  H01L25/18 ,  H01L23/367

    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Innovative Interconnect Design for Package Architecture to Improve Latency
    56.
    发明申请
    Innovative Interconnect Design for Package Architecture to Improve Latency 审中-公开

    公开(公告)号：US20190131268A1

    公开(公告)日：2019-05-02

    申请号：US16023846

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H01L23/00 ,  G06F13/42 ,  G06F13/14 ,  H01L25/065

    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

    Dynamically scalable timing and power models for programmable logic devices
    59.
    发明授权
    Dynamically scalable timing and power models for programmable logic devices 有权

    公开(公告)号：US12273107B2

    公开(公告)日：2025-04-08

    申请号：US17559831

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Atul Maheshwari ,  Mahesh Iyer ,  Mahesh K. Kumashikar ,  Ian Kuon ,  Yuet Li ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H03K19/177 ,  G06F30/34

    Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

    On-die aging measurements for dynamic timing modeling
    60.
    发明授权
    On-die aging measurements for dynamic timing modeling 有权

    公开(公告)号：US12216150B2

    公开(公告)日：2025-02-04

    申请号：US18086616

    申请日：2022-12-21

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

    IPC: G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3193

    Abstract: A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

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