公开(公告)号：US20190165106A1

公开(公告)日：2019-05-30

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/20 ,  H01L29/06 ,  H01L29/04 ,  H01L23/66 ,  H01L29/78 ,  H01L29/205 ,  H01L27/06

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20180219087A1

公开(公告)日：2018-08-02

申请号：US15505911

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20170288022A1

公开(公告)日：2017-10-05

申请号：US15623165

申请日：2017-06-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L29/04 ,  H01L29/786 ,  H01L29/423 ,  H01L27/06 ,  H01L29/205 ,  H01L29/66 ,  H01L23/66

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170133364A9

公开(公告)日：2017-05-11

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L29/94 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/7787 ,  H01L29/94 ,  H01L29/945

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

公开(公告)号：US20160163918A1

公开(公告)日：2016-06-09

申请号：US14906542

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. Chau ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER

IPC: H01L33/06 ,  H01L33/62 ,  H01L33/20 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L27/153 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/16 ,  H01L33/20 ,  H01L33/32 ,  H01L33/325 ,  H01L33/62 ,  H01L2933/0033

Abstract: Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.

Abstract translation: 描述了在硅鳍模板上形成III-V LED结构的方法。 这些方法和结构可以包括在硅鳍片的硅（111）面上形成n掺杂的III-V层，在n掺杂的III-V层上形成量子阱层，形成p掺杂的III-V 层，然后在p掺杂的III-V层上形成欧姆接触层。

公开(公告)号：US20240204059A1

公开(公告)日：2024-06-20

申请号：US18080907

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Michael S. BEUMER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/32 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/32 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: Gallium nitride (GaN) with interlayers for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer including gallium and nitrogen is above the substrate. The layer including gallium and nitrogen has an interlayer therein. The interlayer confines a plurality of defects to a lower portion of the layer including gallium and nitrogen.

公开(公告)号：US20240203979A1

公开(公告)日：2024-06-20

申请号：US18085122

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0266 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based transistor structure is above substrate, the silicon-based transistor structure at a level above the gate of the GaN device in a region outside of the GaN device.

公开(公告)号：US20230081460A1

公开(公告)日：2023-03-16

申请号：US17476310

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Pratik KOIRALA ,  Nityan NAIR ,  Paul B. FISCHER

IPC: G02B6/42 ,  G06F1/16

Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.

公开(公告)号：US20230047449A1

公开(公告)日：2023-02-16

申请号：US17402054

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Nicole K. THOMAS ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Pratik KOIRALA ,  Nityan NAIR

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02

Abstract: Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

公开(公告)号：US20220093683A1

公开(公告)日：2022-03-24

申请号：US17031719

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Ibrahim BAN ,  Paul B. FISCHER ,  Kimin JUN ,  Paul NORDEEN ,  Pratik KOIRALA ,  Tushar TALUKDAR

IPC: H01L27/20 ,  H01L29/16 ,  H01L29/20 ,  H03H9/02 ,  H03H9/17 ,  H03H9/54 ,  H03H9/56

Abstract: Embodiments disclosed herein include resonators and methods of forming such resonators. In an embodiment a resonator comprises a substrate, where a cavity is disposed into a surface of the substrate, and a piezoelectric film suspended over the cavity. In an embodiment, the piezoelectric film has a first surface and a second surface opposite from the first surface, and the piezoelectric film is single crystalline and has a thickness that is 0.5 μm or less. In an embodiment a first electrode is over the first surface of the piezoelectric film, and a second electrode is over the second surface of the piezoelectric film.