公开(公告)号：US20250040231A1

公开(公告)日：2025-01-30

申请号：US18914863

申请日：2024-10-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220093683A1

公开(公告)日：2022-03-24

申请号：US17031719

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Ibrahim BAN ,  Paul B. FISCHER ,  Kimin JUN ,  Paul NORDEEN ,  Pratik KOIRALA ,  Tushar TALUKDAR

IPC: H01L27/20 ,  H01L29/16 ,  H01L29/20 ,  H03H9/02 ,  H03H9/17 ,  H03H9/54 ,  H03H9/56

Abstract: Embodiments disclosed herein include resonators and methods of forming such resonators. In an embodiment a resonator comprises a substrate, where a cavity is disposed into a surface of the substrate, and a piezoelectric film suspended over the cavity. In an embodiment, the piezoelectric film has a first surface and a second surface opposite from the first surface, and the piezoelectric film is single crystalline and has a thickness that is 0.5 μm or less. In an embodiment a first electrode is over the first surface of the piezoelectric film, and a second electrode is over the second surface of the piezoelectric film.

公开(公告)号：US20230066336A1

公开(公告)日：2023-03-02

申请号：US17458112

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Kimin JUN ,  Thomas HOFF ,  Han Wui THEN ,  Nicole K. THOMAS ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

IPC: H01L27/06 ,  H01L29/26 ,  H01L23/48 ,  H01L49/02 ,  H01L29/778 ,  H01L29/04 ,  H01L21/8258 ,  H01L21/822

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：US20230054719A1

公开(公告)日：2023-02-23

申请号：US17408025

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Souvik GHOSH ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Ibrahim BAN ,  Kimin JUN ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/20

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

公开(公告)号：US20230090106A1

公开(公告)日：2023-03-23

申请号：US17481253

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul B. FISCHER ,  Walid M. HAFEZ ,  Nicole K. THOMAS ,  Nityan NAIR ,  Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Thoe MICHAELOS

IPC: H01L29/04 ,  H01L27/092 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/12 ,  H01L21/84

Abstract: Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.

公开(公告)号：US20230069054A1

公开(公告)日：2023-03-02

申请号：US17410257

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Souvik GHOSH ,  Han Wui THEN ,  Pratik KOIRALA ,  Tushar TALUKDAR ,  Paul NORDEEN ,  Nityan NAIR ,  Marko RADOSAVLJEVIC ,  Ibrahim BAN ,  Kimin JUN ,  Jay GUPTA ,  Paul B. FISCHER ,  Nicole K. THOMAS ,  Thomas HOFF ,  Samuel James BADER

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66

Abstract: Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

公开(公告)号：US20220102344A1

公开(公告)日：2022-03-31

申请号：US17033509

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/092 ,  H01L29/40 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06 ,  H01L23/538

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220102339A1

公开(公告)日：2022-03-31

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.