公开(公告)号：US20240213140A1

公开(公告)日：2024-06-27

申请号：US18088541

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ibrahim BAN ,  Nityan NAIR ,  Thomas HOFF

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226

Abstract: Structures having backside high voltage capacitors for front side GaN-based devices are described. In an example, an integrated circuit structure includes a front side structure including a GaN-based device layer, and one or more metallization layers above the GaN-based device layer. A backside structure is below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

公开(公告)号：US20250040231A1

公开(公告)日：2025-01-30

申请号：US18914863

申请日：2024-10-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20240213331A1

公开(公告)日：2024-06-27

申请号：US18088542

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Pratik KOIRALA ,  Wesley HARRISON ,  Marko RADOSAVLJEVIC

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/2003 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7838

Abstract: Gallium nitride (GaN) layer on substrate carburization for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer comprising silicon and carbon is above the substrate. A layer comprising gallium and nitrogen is on the layer comprising silicon and carbon.

公开(公告)号：US20240213118A1

公开(公告)日：2024-06-27

申请号：US18088545

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Heli Chetanbhai VORA ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Thomas HOFF ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Paul NORDEEN ,  Nityan NAIR

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01P3/00

CPC classification number: H01L23/481 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01P3/003 ,  H01L2223/6627

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

公开(公告)号：US20240021725A1

公开(公告)日：2024-01-18

申请号：US18088546

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ahmad ZUBAIR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L29/66462 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/4236

Abstract: Gallium nitride (GaN) transistors with lateral depletion for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen above a silicon substrate, a gate structure over the layer including gallium and nitrogen, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, and a source field plate laterally between the gate structure and the drain region, the source field plate laterally separated from the gate structure.

公开(公告)号：US20230066336A1

公开(公告)日：2023-03-02

申请号：US17458112

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Kimin JUN ,  Thomas HOFF ,  Han Wui THEN ,  Nicole K. THOMAS ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

IPC: H01L27/06 ,  H01L29/26 ,  H01L23/48 ,  H01L49/02 ,  H01L29/778 ,  H01L29/04 ,  H01L21/8258 ,  H01L21/822

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：US20230054719A1

公开(公告)日：2023-02-23

申请号：US17408025

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Souvik GHOSH ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Ibrahim BAN ,  Kimin JUN ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/20

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

公开(公告)号：US20240204059A1

公开(公告)日：2024-06-20

申请号：US18080907

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Michael S. BEUMER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/32 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/32 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: Gallium nitride (GaN) with interlayers for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer including gallium and nitrogen is above the substrate. The layer including gallium and nitrogen has an interlayer therein. The interlayer confines a plurality of defects to a lower portion of the layer including gallium and nitrogen.

公开(公告)号：US20230081460A1

公开(公告)日：2023-03-16

申请号：US17476310

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Pratik KOIRALA ,  Nityan NAIR ,  Paul B. FISCHER

IPC: G02B6/42 ,  G06F1/16

Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.

公开(公告)号：US20230047449A1

公开(公告)日：2023-02-16

申请号：US17402054

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Nicole K. THOMAS ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Pratik KOIRALA ,  Nityan NAIR

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02

Abstract: Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.