公开(公告)号：US20170060205A1

公开(公告)日：2017-03-02

申请号：US14836780

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26 ,  H02J1/00 ,  G06F1/32 ,  H02M3/158

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract translation: 描述了一种装置，其包括：耦合到第一一个或多个电感器的第一电压调节器（VR），第一VR为第一功率域提供电力; 以及耦合到第二一个或多个电感器的第二VR，其中至少一个电感器感应耦合到所述第一个或多个电感器中的至少一个，所述第二VR为与所述第一电源域分离的第二电力域提供电力， 其中在第一VR相对于第二VR的开关晶体管之间存在非零相位角偏移。

公开(公告)号：US12068684B2

公开(公告)日：2024-08-20

申请号：US17030132

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Christopher Schaef ,  William J. Lambert ,  Kaladhar Radhakrishnan

IPC: H02M3/04 ,  H01F27/24 ,  H01L49/02 ,  H03K19/21

CPC classification number: H02M3/04 ,  H01F27/24 ,  H01L28/10 ,  H03K19/21

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US11791528B2

公开(公告)日：2023-10-17

申请号：US17714957

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

CPC classification number: H01P3/082 ,  H01P3/02 ,  H01P3/026 ,  H01P3/06 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088 ,  H05K1/0245

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US11688729B2

公开(公告)日：2023-06-27

申请号：US16030196

申请日：2018-07-09

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Krishna Bharath ,  Mathew Manusharow

IPC: H01L27/01 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L23/49816 ,  H01L23/49827 ,  H01L28/87 ,  H01L28/91

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US11676950B2

公开(公告)日：2023-06-13

申请号：US16635147

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC: H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L25/16 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/642 ,  H01L23/645

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20230060727A1

公开(公告)日：2023-03-02

申请号：US17412810

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Krishna Bharath ,  William J. Lambert ,  Adel A. Elsherbini ,  Sriram Srinivasan ,  Christopher Schaef

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

公开(公告)号：US20220406701A1

公开(公告)日：2022-12-22

申请号：US17822200

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  G05F1/46 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

公开(公告)号：US11527483B2

公开(公告)日：2022-12-13

申请号：US16024717

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Krishna Bharath

IPC: H01L23/538 ,  H01L23/13 ,  H01L51/10 ,  H01L23/367 ,  H01L23/373 ,  H01F27/28 ,  H01L21/48 ,  H01L51/00 ,  H01L23/00 ,  H01L25/16 ,  H01L29/786

Abstract: Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.