公开(公告)号：US20170344424A1

公开(公告)日：2017-11-30

申请号：US15681387

申请日：2017-08-20

Applicant: Intel Corporation

Inventor： John B. HALBERT ,  Kuljit S. BAINS

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/04 ,  G11C11/40 ,  G11C29/56

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

公开(公告)号：US20170194962A1

公开(公告)日：2017-07-06

申请号：US15462664

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Nadav BONEN ,  Christopher E. COX ,  Alexey KOSTINSKY

IPC: H03K19/00 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US20170169880A1

公开(公告)日：2017-06-15

申请号：US15184944

申请日：2016-06-16

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Shay FUX ,  John B. HALBERT

IPC: G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

公开(公告)号：US20240241778A1

公开(公告)日：2024-07-18

申请号：US18562237

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Kuljit S. BAINS ,  Ugonna ECHERUO ,  Reza E. DAFTARI ,  Theodros YIGZAW ,  Mariusz ORIOL

IPC: G06F11/07

CPC classification number: G06F11/073 ,  G06F11/079 ,  G06F11/0793

Abstract: A system (204) can respond to detection of an uncorrectable error (UE) (254) in memory (246) based on fault-aware analysis. The fault-aware analysis enables the system (204) to generate a determination of a specific hardware element of the memory (246) that caused the detected UE (254). In response to detection of a UE (254), the system (204) can correlate a hardware configuration (256) of the memory (246) device with historical data indicating memory (246) faults for hardware elements of the hardware configuration (256). Based on a determination of the specific component that likely caused the UE (254), the system (204) can issue a corrective action for the specific hardware element based on the determination.

公开(公告)号：US20240211344A1

公开(公告)日：2024-06-27

申请号：US18025868

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Kjersten E. CRISS ,  Rajat AGARWAL ,  Omar AVELAR SUAREZ ,  Subhankar PANDA ,  Theodros YIGZAW ,  Rebecca Z. LOOP ,  John G. HOLM ,  Gaurav PORWAL

IPC: G06F11/10 ,  G11C29/02

CPC classification number: G06F11/106 ,  G11C29/02

Abstract: A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

公开(公告)号：US20240061741A1

公开(公告)日：2024-02-22

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Hsing-Min CHEN ,  Wei P. CHEN ,  Wei WU ,  Jing LING ,  Kuljit S. BAINS ,  Kjersten E. CRISS ,  Deep K. BUCH ,  Theodros YIGZAW ,  John G. HOLM ,  Andrew M. RUDOFF ,  Vaibhav SINGH ,  Sreenivas MANDAVA

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20240013851A1

公开(公告)日：2024-01-11

申请号：US18372605

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Hang CHEN ,  Shen ZHOU ,  Kuljit S. BAINS ,  Mohan J. KUMAR ,  Antonio J. HASBUN MARIN

IPC: G11C29/52 ,  G11C29/00 ,  G11C11/406

CPC classification number: G11C29/52 ,  G11C29/883 ,  G11C11/40618

Abstract: A system provides DO-level sparing to spare a fault of a data signal (DQ) line of a memory bus. The data bus has multiple data dynamic random access memory (DRAM) devices and at least one error correction code (ECC) DRAM device coupled to it. An error manager can be in the memory controller or in a platform error controller. The error manager to detect a DQ failure and dynamically switches ECC mode on the fly. The error manager can map out data bits of the DQ and remap ECC bits of the at least one ECC DRAM device to the mapped out data bits of the DQ.

公开(公告)号：US20220350500A1

公开(公告)日：2022-11-03

申请号：US17855688

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Wei P. CHEN ,  Theodros YIGZAW ,  Sarathy JAYAKUMAR ,  Anthony LUCK ,  Deep K. BUCH ,  Rajat AGARWAL ,  Kuljit S. BAINS ,  John G. HOLM ,  Brent CHARTRAND ,  Keith KLAYMAN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.

公开(公告)号：US20220121398A1

公开(公告)日：2022-04-21

申请号：US17561598

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS

IPC: G06F3/06 ,  G11C11/406

Abstract: A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.

公开(公告)号：US20210365316A1

公开(公告)日：2021-11-25

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS ,  Lawrence BLANKENBECKLER ,  Ronald ANDERSON ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/406

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.