公开(公告)号：US20150110193A1

公开(公告)日：2015-04-23

申请号：US14578990

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： Zhipin Deng ,  Yi-Jen Chiu ,  Lidong Xu ,  Wenhao Zhang ,  Yu Han ,  Xiaoxia Cai

IPC: H04N19/51 ,  H04N19/176

CPC classification number: H04N19/51 ,  H04N13/161 ,  H04N19/103 ,  H04N19/119 ,  H04N19/122 ,  H04N19/157 ,  H04N19/176 ,  H04N19/187 ,  H04N19/30 ,  H04N19/463 ,  H04N19/597 ,  H04N19/61 ,  H04N19/96

Abstract: A three-dimensional (3D) video codec encodes multiple views of a 3D video, each including texture and depth components. The encoders of the codec encode video blocks of their respective views based on a set of prediction parameters, such as quad-tree split flags, prediction modes, partition sizes, motion fields, inter directions, reference indices, luma intra modes, and chroma intra modes. The prediction parameters may be inherited across different views and different ones of the texture and depth components.

Abstract translation: 三维（3D）视频编解码器编码3D视频的多个视图，每个视图包括纹理和深度分量。 编解码器基于一组预测参数，例如四叉树分割标志，预测模式，分区大小，运动场，帧间方向，参考索引，亮度帧内模式和色度帧内编码来对其各自视图的视频块进行编码。 模式。 预测参数可以在不同视图和不同的纹理和深度分量之间继承。

公开(公告)号：US20250103430A1

公开(公告)日：2025-03-27

申请号：US18907092

申请日：2024-10-04

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US20240331168A1

公开(公告)日：2024-10-03

申请号：US18309534

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： James Holland ,  Muhammad Hamdan ,  Timothy Chong ,  Lidong Xu ,  Yang Zhou

IPC: G06T7/246

CPC classification number: G06T7/248 ,  G06T2207/10016 ,  G06T2207/20084

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to determine confidence of motion vectors. Examples disclosed herein are to generate feature data associated with a motion vector, the motion vector generated based on a first block of pixel data in a first video frame and a second block of pixel data in a second video frame, determine a confidence score for the motion vector based on a model and the feature data, and concatenate the motion vector and the confidence score to output an estimated likelihood that the motion vector is accurate.

公开(公告)号：US11303923B2

公开(公告)日：2022-04-12

申请号：US16437158

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Zhipin Deng ,  Lidong Xu

IPC: H04N19/523 ,  H04N19/573 ,  H04N19/543 ,  H04N19/52 ,  H04N19/597

Abstract: Embodiments are generally directed to affine motion compensation for current picture referencing. An embodiment of an apparatus includes one or more processors for processing of data; a memory for storage of data including video data; and an encoder for encoding of video data to generate encoded video data, wherein the encoder includes a component to provide affine motion compensation for current picture references in the video data.

公开(公告)号：US11025913B2

公开(公告)日：2021-06-01

申请号：US16400882

申请日：2019-05-01

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC: H04N19/176 ,  H04N19/147 ,  H04N19/567 ,  H04N19/124 ,  H04N19/105

Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20210099727A1

公开(公告)日：2021-04-01

申请号：US17094742

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Zhipin Deng ,  Iole Moccagatta ,  Lidong Xu ,  Wenhao Zhang ,  Yi-Jen Chiu

IPC: H04N19/51 ,  G06T7/238 ,  H04N19/57 ,  H04N19/176 ,  H04N19/593

Abstract: Techniques related to motion estimation with neighbor block pattern for video coding.

公开(公告)号：US20190297344A1

公开(公告)日：2019-09-26

申请号：US16440159

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/533 ,  H04N19/159 ,  H04N19/60 ,  H04N19/88 ,  H04N19/70 ,  H04N19/176

Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

公开(公告)号：US20190261001A1

公开(公告)日：2019-08-22

申请号：US16400882

申请日：2019-05-01

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC: H04N19/147 ,  H04N19/176 ,  H04N19/105 ,  H04N19/124 ,  H04N19/567

Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20190132605A1

公开(公告)日：2019-05-02

申请号：US16300290

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Zhipin Deng ,  Iole Moccagatta ,  Lidong Xu ,  Wenhao Zhang ,  Yi-Jen Chiu

IPC: H04N19/51 ,  H04N19/176 ,  H04N19/593

Abstract: Techniques related to motion estimation with neighbor block pattern for video coding.

公开(公告)号：US20190037227A1

公开(公告)日：2019-01-31

申请号：US15663134

申请日：2017-07-28

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Lidong Xu ,  Fangwen Fu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC: H04N19/43 ,  H04N19/53 ,  H04N19/567 ,  H04N19/115 ,  H04N19/61 ,  H04N19/126 ,  H04N19/96 ,  H04N19/192 ,  H04N19/557

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.