公开(公告)号：US11355623B2

公开(公告)日：2022-06-07

申请号：US15924407

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/49 ,  H01L29/40 ,  G06N10/00 ,  H01L29/423 ,  H01L21/266 ,  B82Y10/00 ,  H01L29/76 ,  H01L21/265 ,  B82Y30/00 ,  B82Y40/00

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

公开(公告)号：US11335778B2

公开(公告)日：2022-05-17

申请号：US16018751

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L21/311 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US20220013658A1

公开(公告)日：2022-01-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US11107891B2

公开(公告)日：2021-08-31

申请号：US16650299

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Kanwaljit Singh ,  Roza Kotlyar ,  Patrick H. Keys ,  James S. Clarke

IPC: H01L29/15 ,  G06N10/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.

公开(公告)号：US20200279937A1

公开(公告)日：2020-09-03

申请号：US16645962

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Kanwaljit Singh ,  Nicole K. Thomas ,  Hubert C. George ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Payam Amin ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/165 ,  G06N10/00 ,  H01L29/423 ,  H01L27/088

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

公开(公告)号：US10714604B2

公开(公告)日：2020-07-14

申请号：US16017031

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Hubert C. George ,  David J. Michalak ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66 ,  H01L29/15 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/12 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/76 ,  H01L29/423 ,  H01L21/308 ,  H01L29/51 ,  H01L29/43 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

公开(公告)号：US20190044050A1

公开(公告)日：2019-02-07

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/04 ,  H01L39/24 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

公开(公告)号：US20190043974A1

公开(公告)日：2019-02-07

申请号：US15900655

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke ,  Willy Rachmady

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US20190043955A1

公开(公告)日：2019-02-07

申请号：US16146899

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L21/02

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.

公开(公告)号：US20190043953A1

公开(公告)日：2019-02-07

申请号：US16144148

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/51 ,  H01L23/522

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a multi-spacer between the first gate and the second gate, wherein the multi-spacer includes a first spacer and a second spacer different from the first spacer, and the first spacer is at least partially between the quantum well stack and the second spacer.