公开(公告)号：US08653896B2

公开(公告)日：2014-02-18

申请号：US13267138

申请日：2011-10-06

Applicant: Kazutaka Takagi ,  Naotaka Tomita

Inventor： Kazutaka Takagi ,  Naotaka Tomita

IPC: H03F3/14

CPC classification number: H03F3/60 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/1305 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/0261 ,  H03F1/565 ,  H03F2200/387 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A class-AB power amplifier according to the present embodiment includes an amplifying element whose power supply voltage is expressed as Vdc and whose maximum current is expressed as Imax, a conduction angle θo of the amplifying element being more than π(rad) and less than 2·π(rad), and load impedance of a fundamental wave being expressed as Z1=R1+j·X1, load impedance of a 2nd harmonic being expressed as Z2=R2+j·X2, and load impedance of a 3rd harmonic being expressed as Z3=R3+j−X3 which are observed from a dependent current source of an equivalent circuit of the amplifying element, and a relationship between variables X1 and R1 is set to −0.5·R1

Abstract translation: 根据本实施例的AB类功率放大器包括其电源电压表示为Vdc并且其最大电流表示为Imax的放大元件，放大元件的导通角θo大于pi（rad）且小于 2·pi（rad），基波的负载阻抗表示为Z1 = R1 + j·X1，二次谐波的负载阻抗表示为Z2 = R2 + j·X2，三次谐波的负载阻抗为 表示为从放大元件的等效电路的依赖电流源观察到的Z3 = R3 + j-X3，变量X1和R1之间的关系设置为-0.5·R1 <= X1 <= 0.5·R1， 变量R1设定为R1 = Vdc / Imax·{1-cos（thetao / 2）}·pi /（θo/ 2-sin（θo）/ 2），变量X2 / X1设定为X2 / X1 = -2 ·{theta-sin（θo）} / {sin（θo/ 2）-sin（1.5·θo）/ 3}，变量X3 / X1设定为X3 / X1 = {theta-sin（θo）} / sin（θo）/ 3-sin（2θo）/ 6}，或者将每个变量设置成为 相等。

公开(公告)号：US08637873B2

公开(公告)日：2014-01-28

申请号：US13164155

申请日：2011-06-20

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L29/04

CPC classification number: H01L23/047 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16747 ,  H01L2924/173 ,  H01L2924/177 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.

Abstract translation: 根据一个实施例，提供了一种用于其的封装和高频端子结构，包括：导电基板; 设置在导电基板上的半导体器件; 设置在所述导电基板上以容纳所述半导体器件的金属壁; 设置在金属壁的输入和输出单元中的通孔; 下层进料通过插入通孔并设置在导电基板上; 并且通过设置在下层上的上层进料通过并附着在金属壁的侧壁上。 下层进料通过金属壁包围。

公开(公告)号：US08610507B2

公开(公告)日：2013-12-17

申请号：US13331513

申请日：2011-12-20

Applicant: Choon Yong Ng ,  Kazutaka Takagi

Inventor： Choon Yong Ng ,  Kazutaka Takagi

IPC: H03F3/14

CPC classification number: H03F3/195 ,  H01L22/32 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6683 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48151 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/1423 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03F1/56 ,  H03F3/245 ,  H03F3/601 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/429 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.

Abstract translation: 根据实施例，功率放大器包括：MMIC衬底; 设置在MMIC衬底上的高频探针焊盘; 以及设置在MMIC基板上以与高频探针焊盘相邻并且经由接合线连接到MMIC外部电路的金属板。

公开(公告)号：US08427248B2

公开(公告)日：2013-04-23

申请号：US12417089

申请日：2009-04-02

Applicant: Choon Yong Ng ,  Kazutaka Takagi ,  Naotaka Tomita

Inventor： Choon Yong Ng ,  Kazutaka Takagi ,  Naotaka Tomita

IPC: H03B9/12 ,  H03B7/06

CPC classification number: H03F3/245 ,  H03F1/086 ,  H03F3/195 ,  H03F2200/391 ,  H03F2200/451

Abstract: A stabilization network and a semiconductor device having the stabilization network wherein the stabilization network includes an active element having a negative resistance accompanying a high frequency negative resistance oscillation; and a tank circuit composed of a resistance connected to a main electrode of the active element, an inductance and capacitance which are connected in parallel with the resistance and synchronize with an oscillating frequency of the high frequency negative resistance oscillation, wherein the stabilization network is performed for suppressing a negative resistance accompanying a Gunn oscillation and obtaining stable and highly efficient power amplification.

Abstract translation: 一种稳定网络和具有稳定网络的半导体器件，其中稳定网络包括具有伴随高频负电阻振荡的负电阻的有源元件; 以及由与有源元件的主电极连接的电阻构成的振荡电路，与电阻并联连接并与高频负电阻振荡的振荡频率同步的电感和电容，其中执行稳定网络 用于抑制伴随Gunn振荡的负电阻并获得稳定和高效的功率放大。

公开(公告)号：US20120268211A1

公开(公告)日：2012-10-25

申请号：US13331513

申请日：2011-12-20

Applicant: Choon Yong Ng ,  Kazutaka Takagi

Inventor： Choon Yong Ng ,  Kazutaka Takagi

IPC: H03F3/213 ,  H03F3/195

CPC classification number: H03F3/195 ,  H01L22/32 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6683 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48151 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/1423 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03F1/56 ,  H03F3/245 ,  H03F3/601 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/429 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.

Abstract translation: 根据实施例，功率放大器包括：MMIC衬底; 设置在MMIC衬底上的高频探针焊盘; 以及设置在MMIC基板上以与高频探针焊盘相邻并且经由接合线连接到MMIC外部电路的金属板。

公开(公告)号：US08154079B2

公开(公告)日：2012-04-10

申请号：US12300795

申请日：2007-11-28

Applicant: Keiichi Matsushita ,  Kazutaka Takagi ,  Naotaka Tomita

Inventor： Keiichi Matsushita ,  Kazutaka Takagi ,  Naotaka Tomita

IPC: H01L31/113

CPC classification number: H01L29/7787 ,  H01L27/0251 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725

Abstract: A semiconductor device, which can prevent an element breakdown by alleviating of electric field concentrations, and can also prevent reduction of gain, includes: a source electrode formed on a semiconductor layer; a drain electrode formed on the semiconductor layer; a gate electrode formed between the source electrode and the drain electrode; an insulating film formed on the semiconductor layer and the gate electrode; a field plate electrode formed on the insulating film; and a resistor for connecting the field plate electrode and the source electrode.

Abstract translation: 可以通过减少电场浓度来防止元件击穿并且还可以防止增益的降低的半导体器件包括：形成在半导体层上的源电极; 形成在半导体层上的漏电极; 形成在源电极和漏电极之间的栅电极; 形成在所述半导体层和所述栅电极上的绝缘膜; 形成在绝缘膜上的场板电极; 以及用于连接场板电极和源电极的电阻器。

公开(公告)号：US08115554B2

公开(公告)日：2012-02-14

申请号：US13211806

申请日：2011-08-17

Applicant: Choon Young Ng ,  Kazutaka Takagi ,  Naotaka Tomita

Inventor： Choon Young Ng ,  Kazutaka Takagi ,  Naotaka Tomita

IPC: H03F3/68

CPC classification number: H03F1/086 ,  H03F1/14 ,  H03F3/193 ,  H03F3/211

Abstract: According to one embodiment, there is a semiconductor device including a first active element, a second active element connected in parallel with the first active element, and a first stabilization circuit connected between a gate of the first active element and a gate of the second active element and configured with a parallel circuit of a gate bypass resistor, a gate bypass capacitor, and a gate bypass inductor, the first stabilization circuit having a resonant frequency equal to an odd mode resonant frequency.

Abstract translation: 根据一个实施例，存在包括第一有源元件，与第一有源元件并联连接的第二有源元件的半导体器件，以及连接在第一有源元件的栅极和第二有源元件的栅极之间的第一稳定电路 元件，并配置有栅极旁路电阻器，栅极旁路电容器和栅极旁路电感器的并联电路，第一稳定电路具有等于奇数模式谐振频率的谐振频率。

公开(公告)号：US20120032190A1

公开(公告)日：2012-02-09

申请号：US13088722

申请日：2011-04-18

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L29/161 ,  H01L29/20 ,  H01L21/50 ,  H01L23/373

CPC classification number: H01L23/3735 ,  H01L23/057 ,  H01L23/3733 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/772 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/142 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, provided are a package utilized for a high frequency semiconductor device and a fabrication method for such the package, the package including: a conductive base plate including a CTE control layer composed of compound material, and a heat conduction layer disposed on the CTE control layer and composed of Cu.

Abstract translation: 根据一个实施例，提供了一种用于高频半导体器件的封装和用于这种封装的制造方法，封装包括：导电基板，其包括由复合材料构成的CTE控制层，以及设置在 CTE控制层由Cu组成。

公开(公告)号：US08097906B2

公开(公告)日：2012-01-17

申请号：US12294620

申请日：2007-10-23

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L23/48 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L24/49 ,  H01L23/4821 ,  H01L23/4824 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/19051 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device which has low input inductance is provided.It includes: source finger electrodes (3) disposed by predetermined direction on the main substrate 1; drain finger electrodes (4) placed and disposed a predetermined interval to each of the source finger electrodes (3); gate finger electrodes (2) disposed between the source finger electrodes (3) and the drain finger electrodes (4), respectively; source pads (6) placed and disposed a predetermined interval at one side of finger electrode array; drain pads (7) disposed between the source pads (6); gate pads (5) which placed and disposed a predetermined interval at the another side of the finger electrode array; source electrode wirings (source bus-line LS, source bridge-line NS and source bridge-line M) for connecting the source finger electrodes (3) to the source pads (6); drain electrode wirings (drain bus-line LD, the drain bridge-line ND, and the drain bridge-line P) for connecting the drain finger electrodes (4) to the drain pads (7); and gate bus-lines for connecting the gate finger electrodes (2) to the gate pads (5).

Abstract translation: 提供具有低输入电感的半导体器件。 它包括：在主衬底1上沿预定方向设置的源极电极（3）; 漏极指电极（4）以预定间隔放置并设置到每个源极指状电极（3）; 分别设置在源极电极（3）和漏极指状电极（4）之间的栅极指状电极（2） 源极焊盘（6）以指状电极阵列的一侧放置和设置预定间隔; 设置在源极焊盘（6）之间的漏极焊盘（7）; 栅极焊盘（5），其在指状电极阵列的另一侧以预定间隔放置和设置; 用于将源极电极（3）连接到源极焊盘（6）的源电极布线（源极总线LS，源桥线NS和源极桥线M）; 用于将漏极指状电极（4）连接到漏极焊盘（7）的漏电极布线（漏极总线LD，漏极桥线ND和漏极桥接线P）; 以及用于将栅极指状电极（2）连接到栅极焊盘（5）的栅极总线。

公开(公告)号：US08022769B2

公开(公告)日：2011-09-20

申请号：US12780280

申请日：2010-05-14

Applicant: Choon Yong Ng ,  Kazutaka Takagi ,  Naotaka Tomita

Inventor： Choon Yong Ng ,  Kazutaka Takagi ,  Naotaka Tomita

IPC: H03F3/68

CPC classification number: H03F1/086 ,  H03F1/14 ,  H03F3/193 ,  H03F3/211

Abstract: According to one embodiment, there is a semiconductor device including a first active element, a second active element connected in parallel with the first active element, and a first stabilization circuit connected between a gate of the first active element and a gate of the second active element and configured with a parallel circuit of a gate bypass resistor, a gate bypass capacitor, and a gate bypass inductor, the first stabilization circuit having a resonant frequency equal to an odd mode resonant frequency.

Abstract translation: 根据一个实施例，存在包括第一有源元件，与第一有源元件并联连接的第二有源元件的半导体器件，以及连接在第一有源元件的栅极和第二有源元件的栅极之间的第一稳定电路 元件，并配置有栅极旁路电阻器，栅极旁路电容器和栅极旁路电感器的并联电路，第一稳定电路具有等于奇数模式谐振频率的谐振频率。