公开(公告)号：US20220206941A1

公开(公告)日：2022-06-30

申请号：US17698424

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Ning Chen ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F12/02 ,  G06F3/06

Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units. Data located in data management units subsequent to the second indicator remain located in data management units of the source group of data management units and have not been copied to the destination group of data management units.

公开(公告)号：US20220019383A1

公开(公告)日：2022-01-20

申请号：US17492181

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Alex Tang

IPC: G06F3/06 ,  G06F11/10 ,  G06F13/16

Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.

公开(公告)号：US20210089218A1

公开(公告)日：2021-03-25

申请号：US17114380

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ning Chen ,  Ying Yu Tai

IPC: G06F3/06 ,  G06F12/10

Abstract: Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received. A physical address based on the base address of the first group of data blocks and the logical address is determined. The subsequent data is accessed at the first group of data blocks based on the physical address.

公开(公告)号：US20210019254A1

公开(公告)日：2021-01-21

申请号：US16797650

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Ning Chen ,  Fangfang Zhu ,  Alex Tang

IPC: G06F12/02 ,  G06F11/30 ,  G11C16/34

Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.

公开(公告)号：US20210019058A1

公开(公告)日：2021-01-21

申请号：US16874389

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Alex Tang

IPC: G06F3/06

Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.

公开(公告)号：US20200065007A1

公开(公告)日：2020-02-27

申请号：US16110739

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu

IPC: G06F3/06 ,  G06F12/10

Abstract: A memory sub-system performs a first wear leveling operation among a plurality of individual data units of the memory component after a first interval and performs a second wear leveling operation among a first plurality of groups of data units of the memory component after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units. The memory sub-system further performs a third wear leveling operation among a second plurality of groups of data units of the memory component after a third interval, wherein a second group of the second plurality of groups comprises the first plurality of groups of data units.