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    PARTIALLY PROGRAMMED BLOCK READ OPERATIONS
    51.
    发明公开
    PARTIALLY PROGRAMMED BLOCK READ OPERATIONS 审中-公开

    公开(公告)号：US20240303187A1

    公开(公告)日：2024-09-12

    申请号：US18591368

    申请日：2024-02-29

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Ryan Hrinya ,  Fulvio Rori ,  Scott A. Stoller ,  Tyler Betz

    IPC: G06F12/02

    CPC classification number: G06F12/0246

    Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in an array of memory cells during a read operation on the word line, apply a first pass voltage to a number of programmed word lines in the array of memory cells during the read operation, and apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells during the read operation.

    DYNAMIC ERASE VOLTAGE STEP
    52.
    发明公开
    DYNAMIC ERASE VOLTAGE STEP 审中-公开

    公开(公告)号：US20240281148A1

    公开(公告)日：2024-08-22

    申请号：US18443584

    申请日：2024-02-16

    Applicant: Micron Technology, Inc.

    Inventor： Jiun-Horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Ronit Roneel Prakash ,  Yoshiaki Fukuzumi

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.

    DYNAMIC WORD LINE ALLOCATION IN MEMORY SYSTEMS
    54.
    发明公开
    DYNAMIC WORD LINE ALLOCATION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20240249789A1

    公开(公告)日：2024-07-25

    申请号：US18417517

    申请日：2024-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Tarun Singh Yadav ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Fulvio Rori ,  Attila A. Herrera ,  Justin Bates

    IPC: G11C29/12

    CPC classification number: G11C29/1201 ,  G11C2029/1202

    Abstract: Aspects of the present disclosure configure a memory sub-system controller to adaptively allocate word lines (WLs). The controller accesses reliability data of a set of main WLs of a block of the set of memory components. The controller determines that one or more WLs of the set of main WLs of the block are associated with respective reliability data that transgress a threshold and, in response to determining that the one or more WLs are associated with the respective reliability data that transgress the threshold, replaces the one or more WLs of the set of main WLs of the block with one or more dummy WLs. The controller programs data into the block using the one or more dummy WLs instead of the one or more WLs of the set of main WLs of the block.

    PROGRAM PULSE MODIFICATION
    55.
    发明公开
    PROGRAM PULSE MODIFICATION 审中-公开

    公开(公告)号：US20240248612A1

    公开(公告)日：2024-07-25

    申请号：US18406852

    申请日：2024-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Lei Lin ,  Peng Zhang ,  Pitamber Shukla ,  Zhengang Chen ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.

    DYNAMIC PRIORITIZATION OF SELECTOR VT SCANS
    59.
    发明公开
    DYNAMIC PRIORITIZATION OF SELECTOR VT SCANS 审中-公开

    公开(公告)号：US20230195355A1

    公开(公告)日：2023-06-22

    申请号：US17733460

    申请日：2022-04-29

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Avinash Rajagiri ,  Devin Batutis

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0616 ,  G06F3/0679

    Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

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