Single reference clock time to digital converter

    公开(公告)号:US10715754B2

    公开(公告)日:2020-07-14

    申请号:US15877551

    申请日:2018-01-23

    Abstract: In an embodiment, a TDC includes: a clock input configured to receive a reference clock that is synchronized with a first event; a clock generation circuit configured to generate a first clock at a first output of the clock generation circuit based on the reference clock, the first clock having a second frequency lower than the reference clock; a data input configured to receive an input stream of pulses, where the input stream of pulses is based on the first event; a sampling circuit having an input register, the sampling circuit coupled to the data input, the sampling circuit configured to continuously sample the input stream of pulses into the input register based on the reference clock; and output terminals configured to stream time stamps based on the input stream of pulses at the second frequency, where the stream of time stamps is synchronized with the first clock.

    TIME TO DIGITAL CONVERTER AND APPLICATIONS THEREOF
    55.
    发明申请
    TIME TO DIGITAL CONVERTER AND APPLICATIONS THEREOF 有权
    数字转换器及其应用

    公开(公告)号:US20150041625A1

    公开(公告)日:2015-02-12

    申请号:US14451482

    申请日:2014-08-05

    CPC classification number: G04F10/005 G01S7/4865 G01S17/10 G01T1/248 G01T1/2985

    Abstract: A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs.

    Abstract translation: 时间到数字转换器包括可操作以在多个不同的时间点对输入信号进行采样的采样模块。 由比较元件形成的转换检测模块在连续的时间实例处理采样的输入信号,以便检测输入信号在时间上的转变。 输出模块在多个并行输出上产生输入信号中检测到的转换。

    TOF SYSTEM
    58.
    发明申请

    公开(公告)号:US20220390576A1

    公开(公告)日:2022-12-08

    申请号:US17341084

    申请日:2021-06-07

    Abstract: In an embodiment, a method includes: resetting respective count values of a plurality of analog counters to an initial count value, each analog counter of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; after resetting the respective count values, receiving a plurality of digital addresses from a time-to-digital converter (TDC); during an integration period, for each received digital address, selecting one analog counter based on the received digital address, and changing the respective count value of the selected one analog counter towards a second count value by a discrete amount, where each analog counter has a final count value at an end of the integration period; and after the integration period, determining an associated final bin count of each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

    Routing For DTOF Sensors
    59.
    发明申请

    公开(公告)号:US20220357435A1

    公开(公告)日:2022-11-10

    申请号:US17868261

    申请日:2022-07-19

    Abstract: A ToF sensor includes an array of pixels having first and second subsets of pixels, first and second pluralities of TDCs, a routing bus having first and second pluralities of bus drivers, and a controller configured to: when the first subset of pixels is active and the second subset of pixels is not active, control the first plurality of bus drivers to route events from half of the pixels of the first subset to the first plurality of TDCs and control the first and second pluralities of bus drivers to route events from the other half of the pixels of the first subset to the second plurality of TDCs, and when the first subset of pixels is not active and the second subset of pixels is active, control the first plurality of bus drivers to route events from the second subset of pixels to the first plurality of TDCs.

    Anode sensing circuit for single photon avalanche diodes

    公开(公告)号:US11349042B2

    公开(公告)日:2022-05-31

    申请号:US16718762

    申请日:2019-12-18

    Abstract: A pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage supply through a quenching element, with the SPAD having a capacitance at its anode formed from a deep trench isolation, with the quenching element having a sufficiently high resistance such that the capacitance is not fully charged when the SPAD is struck by an incoming photon. The pixel includes a clamp transistor configured to be controlled by a voltage clamp control signal to clamp voltage at an anode of the SPAD when the SPAD is struck by an incoming photon to be no more than a threshold clamped anode voltage, and readout circuitry coupled to receive the clamped anode voltage from the clamp transistor and to generate a pixel output therefrom. The threshold clamped anode voltage is below a maximum operating voltage rating of transistors forming the readout circuitry.

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