公开(公告)号：US20160118383A1

公开(公告)日：2016-04-28

申请号：US14990141

申请日：2016-01-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi YONEDA

IPC: H01L27/07 ,  H01L23/522 ,  H01L23/535 ,  H01L23/528 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/535 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0733 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41758 ,  H01L29/7869 ,  H01L2924/0002 ,  H02J50/12 ,  H03C2200/0029 ,  H03H7/1741 ,  H03J1/00 ,  H03J3/10 ,  H01L2924/00

Abstract: A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor.

Abstract translation: 半导体器件包括用作线圈的天线，与天线并联电连接的电容器，通过与天线和电容器并联电连接而形成与天线和电容器的谐振电路的无源元件，第一场 效应晶体管，控制无源元件是否并联电连接到天线和电容器，以及存储器电路。 存储电路包括第二场效应晶体管，其包括其中形成沟道并且其中数据信号被输入到源极和漏极中的一个的氧化物半导体层。 第一场效应晶体管的栅极电压根据第二场效应晶体管的源极和漏极中的另一个的电压来设定。

公开(公告)号：US20150061742A1

公开(公告)日：2015-03-05

申请号：US14471322

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yukio Maehashi ,  Seiichi YONEDA ,  Wataru UESUGI

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356 ,  H03K3/356104

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Abstract translation: 存储电路包括第一和第二逻辑电路，其沟道形成区域包括氧化物半导体的第一和第二晶体管以及电容器。 第一和第二晶体管串联连接，电容器连接到第一和第二晶体管的连接节点。 第一晶体管用作控制第一逻辑电路的输出端子和电容器之间的连接的开关。 第二晶体管用作控制电容器和第二逻辑电路的输入端之间的连接的开关。 其相位相互反相的时钟信号被输入到第一和第二晶体管的栅极。 由于存储电路具有少量晶体管和由时钟信号控制的少量晶体管，所以存储电路是低功率电路。

公开(公告)号：US20250014616A1

公开(公告)日：2025-01-09

申请号：US18894175

申请日：2024-09-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeya HIROSE ,  Seiichi YONEDA ,  Takayuki IKEDA ,  Shunpei YAMAZAKI

IPC: G11C7/16 ,  G11C11/40 ,  G11C11/54 ,  G11C27/02 ,  H01L29/786

Abstract: A semiconductor device capable of holding analog data is provided. Two holding circuits, two bootstrap circuits, and one source follower circuit are formed with use of four transistors and two capacitors. A memory node is provided in each of the two holding circuits; a data potential is written to one of the memory nodes and a reference potential is written to the other of the memory nodes. At the time of data reading, the potential of the one memory node is increased in one of the bootstrap circuits, and the potential of the other memory node is increased in the other of the bootstrap circuits. A potential difference between the two memory nodes is output by the source follower circuit. With use of the source follower circuit, the output impedance can be reduced.

公开(公告)号：US20230247331A1

公开(公告)日：2023-08-03

申请号：US17768972

申请日：2020-10-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi YONEDA ,  Hiroki INOUE

IPC: H04N25/78 ,  H04N25/709 ,  H04N25/77

CPC classification number: H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

Abstract: An imaging device with low power consumption is provided. A pixel includes a first circuit and a second circuit. The first circuit can generate imaging data and retain difference data that is a difference between the imaging data and data obtained in an initial frame. The second circuit includes a circuit that compares the difference data and a voltage range set arbitrarily. The second circuit supplies a reading signal based on the comparison result. With the use of the structure, reading from the pixel is not performed when it is determined that the difference data is within the set voltage range and reading from the pixel can be performed when it is determined that the difference data is outside the voltage range.

公开(公告)号：US20230198509A1

公开(公告)日：2023-06-22

申请号：US18008287

申请日：2021-07-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeya HIROSE ,  Seiichi YONEDA ,  Yusuke NEGORO

IPC: H03K3/356

CPC classification number: H03K3/35613 ,  H01L29/78648

Abstract: A semiconductor device with low power consumption can be provided. The semiconductor device includes a differential circuit and a latch circuit, the differential circuit includes a transistor including an oxide semiconductor in a channel formation region, and the latch circuit includes a transistor including a single semiconductor or a compound semiconductor in a channel formation region. The differential circuit and the latch circuit include an overlap region.

公开(公告)号：US20230179888A1

公开(公告)日：2023-06-08

申请号：US18008302

申请日：2021-07-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunsuke SATO ,  Seiichi YONEDA ,  Yusuke NEGORO ,  Takeya HIROSE ,  Shunpei YAMAZAKI

IPC: H04N25/77

CPC classification number: H04N25/77

Abstract: An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel unit, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel unit and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, whereby power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are stacked, so that the lengths of wirings between the circuits can be reduced, and high-speed operation with low power consumption can be performed.

公开(公告)号：US20230090488A1

公开(公告)日：2023-03-23

申请号：US17904115

申请日：2021-02-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiichi YONEDA ,  Hiroki INOUE ,  Yusuke NEGORO ,  Takayuki IKEDA ,  Shunpei YAMAZAKI

IPC: H01L27/146 ,  H01L29/786

Abstract: A small-sized and highly functional imaging device is provided. The imaging device includes a photoelectric conversion device formed on a silicon substrate and a transistor including a channel formation region in a silicon epitaxial growth layer formed on the silicon substrate. The transistor provided in the epitaxial growth layer has favorable electrical characteristics, so that the imaging device with little noise can be formed. Since the transistor can be formed so as to have a region overlapping with the photoelectric conversion device, the imaging device can be downsized.

公开(公告)号：US20220326384A1

公开(公告)日：2022-10-13

申请号：US17634035

申请日：2020-08-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yusuke NEGORO ,  Seiichi YONEDA

IPC: G01S17/89 ,  H01L27/146 ,  H01L31/107 ,  G01B11/22 ,  G01S7/481 ,  G01S7/4865

Abstract: An object is to obtain accurate distance image data by denoising. Another object is to realize distance image data acquisition in a short time by reducing the frequency of accumulating. A distance image processing system including a solid-state imaging element that can be used for three-dimensionally recognizing an object is provided for the utilization of autonomous driving of passenger cars, for example. Image processing including distance information obtained by a TOF system solid-state imaging element, a so-called TOF camera, is performed by utilizing deep learning. A high-accurate distance image with noise reduced by deep learning can be obtained.

公开(公告)号：US20220321794A1

公开(公告)日：2022-10-06

申请号：US17626566

申请日：2020-07-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiichi YONEDA ,  Yusuke NEGORO

IPC: H04N5/232 ,  H01L27/146

Abstract: An imaging device capable of executing image processing is provided. An imaging device with low power consumption is provided. A highly reliable imaging device is provided. An imaging device with higher integration degree of pixels is provided. An imaging device manufactured at low cost is provided. The imaging device includes a photoelectric conversion device, a first transistor that is formed in a first layer and includes silicon in a channel formation layer, and a capacitor that is formed in a second layer bonded to the first layer. One of a source and a drain of the first transistor is electrically connected to one of electrodes of the photoelectric conversion device, and the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. A pixel having a function of generating first data and a function of multiplying the first data to have a given magnification to generate second data is included. The first data and the second data each have an analog value.

公开(公告)号：US20220238582A1

公开(公告)日：2022-07-28

申请号：US17617016

申请日：2020-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi YONEDA ,  Yusuke NEGORO

IPC: H01L27/146

Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and extract data obtained by multiplying the analog data by a predetermined weight coefficient. When the data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.