公开(公告)号：US20210119110A1

公开(公告)日：2021-04-22

申请号：US16656304

申请日：2019-10-17

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.

公开(公告)号：US10978339B2

公开(公告)日：2021-04-13

申请号：US16011615

申请日：2018-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

公开(公告)号：US20210050511A1

公开(公告)日：2021-02-18

申请号：US16563924

申请日：2019-09-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Tai-Cheng Hou ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.

公开(公告)号：US10692758B1

公开(公告)日：2020-06-23

申请号：US16212362

申请日：2018-12-06

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

公开(公告)号：US10679893B2

公开(公告)日：2020-06-09

申请号：US16121605

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.

公开(公告)号：US20180012793A1

公开(公告)日：2018-01-11

申请号：US15713724

申请日：2017-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chich-Neng Chang ,  Ya-Jyuan Hung ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/535 ,  H01L2221/1063

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.

公开(公告)号：US09530696B1

公开(公告)日：2016-12-27

申请号：US14921514

申请日：2015-10-23

Applicant: United Microelectronics Corp.

Inventor： Wei-Hsin Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Wei-Lun Hsu ,  Shang-Yi Yang ,  Pi-Hsuan Lai

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成有多个牺牲栅极和其下的多个牺牲栅介质层。 在牺牲栅极之间填充层间电介质层。 在层间电介质层上形成保护层。 去除牺牲栅极和牺牲栅极电介质层以形成开口，其中层间介电层被保护层保护而不被凹陷。 在开口中形成堆叠的栅极结构，其中保护层被去除。

公开(公告)号：US20250142958A1

公开(公告)日：2025-05-01

申请号：US18534754

申请日：2023-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a SOI substrate having a device layer and a buried oxide layer contiguous with the device layer; a transistor disposed on the device layer; a dielectric layer surrounding the transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the transistor; a charge trapping layer contiguous with the buried oxide layer; a capping layer contiguous with the charge trapping layer; and a conductive via penetrating through the capping layer, the charge trapping layer, the buried oxide layer, the device layer, and the dielectric layer. The conductive via is electrically connected to the interconnect structure.

公开(公告)号：US20250140666A1

公开(公告)日：2025-05-01

申请号：US18539321

申请日：2023-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Tai-Cheng Hou

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a RDL interposer having a first surface and a second surface; fanout pads and peripheral pads on the second surface; a first semiconductor die on the first surface and electrically connected to the fanout pads; a molding compound surrounding the first semiconductor die and the first surface of the RDL interposer; through mold vias in the molding compound around the first semiconductor die; peripheral solder bumps within the through mold vias and directly disposed on the peripheral pads; through silicon via pads on the rear surface of the first semiconductor die; a second semiconductor die bonded to the through silicon via pads of the first semiconductor die and the peripheral solder bumps within the through mold vias.

公开(公告)号：US20250072075A1

公开(公告)日：2025-02-27

申请号：US18946839

申请日：2024-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film