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    Method of fabrication transistor with non-uniform stress layer with stress concentrated regions
    51.
    发明授权
    Method of fabrication transistor with non-uniform stress layer with stress concentrated regions 有权
    具有应力集中区域的具有非均匀应力层的晶体管的制造方法

    公开(公告)号：US09343573B2

    公开(公告)日：2016-05-17

    申请号：US14557469

    申请日：2014-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

    Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

    Abstract translation: 一种制造具有不均匀应力层的晶体管器件的方法，包括以下过程。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层的拉伸应力低于第二拉伸应力层的拉伸应力。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE SAME
    53.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE SAME 有权
    制造半导体器件的方法及其制造的器件

    公开(公告)号：US20150325574A1

    公开(公告)日：2015-11-12

    申请号：US14272672

    申请日：2014-05-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/66

    CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

    Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

    Abstract translation: 提供了一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层，直到到达绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。

    Multigate field effect transistor and process thereof
    54.
    发明授权
    Multigate field effect transistor and process thereof 有权
    多场效应晶体管及其工艺

    公开(公告)号：US09159831B2

    公开(公告)日：2015-10-13

    申请号：US13662561

    申请日：2012-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

    IPC: H01L21/70 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11

    CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

    Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 电介质层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

    Semiconductor process
    55.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US09034726B2

    公开(公告)日：2015-05-19

    申请号：US14285645

    申请日：2014-05-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

    IPC: H01L21/762 ,  H01L29/06

    CPC classification number: H01L21/76224 ,  H01L29/0649

    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

    Abstract translation: 半导体结构位于衬底的凹部中。 半导体结构包括衬垫，富硅层和填充材料。 衬垫位于凹槽的表面上。 富硅层位于衬套上。 填充材料位于富硅层上并填充凹槽。 此外，还提供了形成所述半导体结构的半导体工艺。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    56.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150064896A1

    公开(公告)日：2015-03-05

    申请号：US14013429

    申请日：2013-08-29

    Applicant: United Microelectronics Corp.

    Inventor： Hung-Lin Shih ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu

    IPC: H01L21/28

    CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

    Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成虚拟栅极结构，其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模，并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层，其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    57.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20140367779A1

    公开(公告)日：2014-12-18

    申请号：US13917623

    申请日：2013-06-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.

    Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于空部分正下方的通孔。 门围绕着空的部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部形成空的部分，从而在通孔上形成空的部分。 形成围绕空闲部分的门。

    ATOMIC LAYER DEPOSITION METHOD
    58.
    发明申请
    ATOMIC LAYER DEPOSITION METHOD 审中-公开
    原子层沉积法

    公开(公告)号：US20140242811A1

    公开(公告)日：2014-08-28

    申请号：US13778147

    申请日：2013-02-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jui-Chen Chang ,  Chen-Kuo Chiang ,  Chin-Fu Lin ,  Chih-Chien Liu

    IPC: H01L21/02

    CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/28194 ,  H01L29/517

    Abstract: An ALD method includes providing a substrate in an ALD reactor, performing a pre-ALD treatment to the substrate in the ALD reactor, and performing one or more ALD cycles to form a dielectric layer on the substrate in the ALD reactor. The pre-ALD treatment includes providing a hydroxylating agent to the substrate in a first duration, and providing a precursor to the substrate in a second duration. Each of the ALD cycles includes providing the hydroxylating agent to the substrate in a third duration, and providing the precursor to the substrate in a fourth duration. The first duration is longer than the third duration.

    Abstract translation: ALD方法包括在ALD反应器中提供衬底，对ALD反应器中的衬底进行预ALD处理，以及执行一个或多个ALD循环以在ALD反应器中的衬底上形成电介质层。 前ALD治疗包括在第一持续时间内向基质提供羟化剂，并在第二持续时间内向基质提供前体。 每个ALD循环包括在第三个持续时间内向基质提供羟基化试剂，并在第四个持续时间内向基质提供前体。 第一个时间长于第三个持续时间。

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