公开(公告)号：US20160372189A1

公开(公告)日：2016-12-22

申请号：US15181009

申请日：2016-06-13

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

Abstract translation: 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

公开(公告)号：US20150262664A1

公开(公告)日：2015-09-17

申请号：US14727190

申请日：2015-06-01

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C13/00

CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

公开(公告)号：US20150222251A1

公开(公告)日：2015-08-06

申请号：US14688060

申请日：2015-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: H03K3/356 ,  G11C8/08 ,  G11C13/00

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

Abstract translation: 公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。 在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。 此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储器单元，其被配置为例如在大于第一电压范围的第二电压范围内操作 。 交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。 集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。 有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

公开(公告)号：US09053756B2

公开(公告)日：2015-06-09

申请号：US14068754

申请日：2013-10-31

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C11/16 ,  G11C5/00 ,  G11C5/02

CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

公开(公告)号：US08854888B2

公开(公告)日：2014-10-07

申请号：US13693214

申请日：2012-12-04

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/34

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

Abstract translation: 公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。 在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。 此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储单元，其被配置为例如在大于第一电压范围的第二电压范围内操作 。 交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。 集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。 有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。