公开(公告)号：US06553511B1

公开(公告)日：2003-04-22

申请号：US09573058

申请日：2000-05-17

Applicant: Rodney A. DeKoning ,  Thomas L. Langford, II ,  Scott E. Greenfield

Inventor： Rodney A. DeKoning ,  Thomas L. Langford, II ,  Scott E. Greenfield

IPC: G06F1100

CPC classification number: G06F11/1076 ,  G06F11/2058 ,  G06F11/2069 ,  G06F11/2082 ,  G06F2201/83 ,  G06F2211/104

Abstract: Sequence number metadata which identifies an input/output (I/O) operation, such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and revision number metadata which identifies an I/O operation such as a read modify write operation on user data recorded in components of the stripe, are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error arising after a full stripe write is detected by a difference in sequence numbers for all of the components of user data in the stripe. An error arising after a read modify write is detected by a revision number which occurred before the correct revision number. The errors in both cases are corrected by using the parity metadata for the entire collection of user data and the correct information from the other components of the user data and metadata, and applying this information to an error correcting algorithm. The technique may be executed in conjunction with a read I/O operation without incurring a substantial computational overhead penalty.

Abstract translation: 识别输入/输出（I / O）操作的序列号元数据，例如在独立磁盘冗余阵列（RAID）大容量存储系统上的完整条带写入，以及标识I / O操作的修订号元数据，例如 对记录在条带组件中的用户数据进行读取修改写操作，用于错误检测和校正技术以及奇偶校验元数据，以检测和纠正由无意数据路径和驱动器数据损坏引起的无声错误。 通过条带中用户数据的所有组件的序列号差异来检测完整条带写入之后出现的错误。 读取修改写入后出现的错误是由正确的版本号之前发生的版本号检测到的。 通过使用用户数据的整个集合的奇偶校验元数据和来自用户数据和元数据的其他组件的正确信息来校正两种情况中的错误，并将该信息应用于纠错算法。 该技术可以结合读取的I / O操作执行，而不会引起实质的计算开销损失。

公开(公告)号：US20030059962A1

公开(公告)日：2003-03-27

申请号：US10151990

申请日：2002-05-21

Inventor： Udo Hartmann ,  Jochen Kallscheuer ,  Peter Beer

IPC: H01L021/66

CPC classification number: G11C29/14 ,  G01R31/30 ,  G06F11/26 ,  G06F2201/83 ,  G11C29/46

Abstract: A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Abstract translation: 描述了用于测试半导体芯片，特别是半导体存储器芯片的方法。 其中，在要测试的芯片中，设置至少一个测试模式，芯片中执行测试模式，并从芯片输出测试结果。 条件是，在设置之后和执行测试模式之前，执行检查模式，其中以定义的格式读出设置在芯片中的测试模式的状态。

公开(公告)号：US06357024B1

公开(公告)日：2002-03-12

申请号：US09132334

申请日：1998-08-12

Applicant: Drew J. Dutton ,  Dan S. Mudgett ,  Scott A. White

Inventor： Drew J. Dutton ,  Dan S. Mudgett ,  Scott A. White

IPC: G06F1100

CPC classification number: G06F11/1654 ,  G06F11/1641 ,  G06F11/165 ,  G06F2201/83

Abstract: An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing “signatures” produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic. The system bus is adapted for coupling to one or more peripheral devices. The chip set logic is coupled between the first and second CPUs and the system bus, and functions as an interface between the first and second CPUs and the system bus. The first and second CPU are coupled to the chip set logic via separate processor buses. At least a portion of the signal lines of the separate processor buses are “point-to-point”, enabling the processor buses to achieve relatively high data transfer rates.

Abstract translation: 通过比较由两个不同的电子设备（例如中央处理单元（CPU））产生的“签名”来呈现用于实现功能冗余检查（FRC）的电子系统和方法。 签名包括反映每个CPU的内部状态的相对较少数量的信号。 该电子系统包括第一和第二CPU。 每个CPU配置为执行指令并产生输出信号。 第一和第二CPU优选地是相同的并且同时执行指令，使得它们的内部状态和产生的输出信号在任何给定的时间应该相同。 每个CPU包括用于生成签名的签名生成器。 电子系统还包括耦合以接收签名的比较单元。 比较单元比较签名并且如果签名不相同则产生错误信号。 电子系统可以是计算机系统，还包括系统总线和芯片组逻辑。 系统总线适于耦合到一个或多个外围设备。 芯片组逻辑耦合在第一和第二CPU与系统总线之间，并且用作第一和第二CPU与系统总线之间的接口。 第一和第二CPU通过单独的处理器总线耦合到芯片组逻辑。 单独处理器总线的信号线的至少一部分是“点到点”，使得处理器总线能够实现相对较高的数据传输速率。

公开(公告)号：US5993055A

公开(公告)日：1999-11-30

申请号：US882863

申请日：1997-06-26

Applicant: Emrys John Williams

Inventor： Emrys John Williams

IPC: G06F11/18 ,  G06F11/22 ,  G06F11/25 ,  G06F11/277 ,  G06F15/16 ,  G06F15/177 ,  G06F11/00

CPC classification number: G06F11/184 ,  G06F11/25 ,  G06F11/277 ,  G06F11/1679 ,  G06F2201/83

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.

Abstract translation: 容错计算机系统包括多个锁步子系统，每个子系统包括并行输入签名生成器，用于数据压缩，以允许对锁步子系统的内部模块的操作进行实际比较;以及逻辑分析器，其存储 锁步子系统的内部模块。 连接签名比较器以从各个锁步子系统的签名生成器接收签名。 签名比较器产生触发信号，用于在检测签名中的差异时触发逻辑分析器。 逻辑分析器存储足够的状态，以便在签名输出中检测到的差异之后包括与模块的第一差异。 逻辑分析仪跟踪在不同步事件后自动搜索，以确定操作中的第一个差异，并确定哪个内部模块提供了有缺陷的输出，然后该模块被标记为损坏。

公开(公告)号：US5964860A

公开(公告)日：1999-10-12

申请号：US831798

申请日：1997-04-08

Applicant: John C. Peterson ,  Edward T. Chow ,  Michael S. Waterman ,  Timothy J. Hunkapillar

Inventor： John C. Peterson ,  Edward T. Chow ,  Michael S. Waterman ,  Timothy J. Hunkapillar

IPC: G06F7/02 ,  G06F11/00 ,  G06F11/267 ,  G06F17/10 ,  G06F19/00

CPC classification number: G06F11/2028 ,  G06F11/2051 ,  G06F17/10 ,  G06F7/02 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2236 ,  G06F2201/83

Abstract: An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

Abstract translation: 电子电路用于比较诸如遗传序列的两个序列，以确定序列的哪个对齐产生最大的相似性。 该电路包括串联连接处理器的线性阵列，每个处理器存储来自一个序列的单个元件，并将该元素与另一个序列中的每个连续元素进行比较。 对于每个比较，处理器产生一个评分参数，该参数指示在那两个元素处结束的哪个段在序列之间产生最大程度的相似度。 处理器使用评分参数来生成相似的评分参数，用于比较存储的元素和来自其他序列的下一个连续元素之间的比较。 处理器还将得分参数提供给阵列中的下一个处理器，以用于为另一对元素生成类似的评分参数。 电子电路确定哪个处理器和序列的对齐产生具有最高值的评分参数。

公开(公告)号：US5825785A

公开(公告)日：1998-10-20

申请号：US653572

申请日：1996-05-24

Applicant: Robert L. Barry ,  John D. Chickanosky ,  Steven F. Oakland ,  Michael R. Ouellette

Inventor： Robert L. Barry ,  John D. Chickanosky ,  Steven F. Oakland ,  Michael R. Ouellette

IPC: G01R31/3181 ,  G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/3185 ,  G01R31/31813 ,  G06F2201/83

Abstract: A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

Abstract translation: 用于嵌入式编译宏的高度内置的自测电路对于测试具有不同参数的嵌入式编译宏非常有用。 内建的自检电路接收一个描述被测试的嵌入式编译宏的参数的扫描向量。 例如，存储在只读存储器（ROM）中的字的数量和宽度被扫描到用于控制测试序列的内置自测试电路中。 内置自检电路中的状态机通过测试向量生成，测试向量应用，数据输出扫描和压缩进行签名分析。 嵌入式编译器件的并行输出被串行化，所以无论输出数量多少，都可以使用串行输入移位寄存器进行签名生成。

公开(公告)号：US5566186A

公开(公告)日：1996-10-15

申请号：US202651

申请日：1994-02-28

Applicant: Barry T. Paterson ,  Kenneth D. Crocker

Inventor： Barry T. Paterson ,  Kenneth D. Crocker

IPC: G01R31/3185 ,  G06F11/00

CPC classification number: G01R31/318536 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/31908 ,  G06F2201/83

Abstract: A test control device for controlling the distribution of test data is connectable in parallel to a plurality of integrated circuits.

Abstract translation: 用于控制测试数据分布的测试控制装置可与多个集成电路并联连接。

公开(公告)号：US5396170A

公开(公告)日：1995-03-07

申请号：US34156

申请日：1993-06-01

Applicant: Daniel D'Souza ,  Ruth Alexander

Inventor： Daniel D'Souza ,  Ruth Alexander

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/319 ,  G01R31/28

CPC classification number: G01R31/3187 ,  G01R31/31858 ,  G01R31/318552 ,  G01R31/319 ,  G06F2201/83

Abstract: An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test. In another embodiment, the test chip is sandwiched between a device under test (DUT) and the PCB on which the DUT is mounted for at speed board test.

Abstract translation: 一种集成电路（IC）测试架构和技术，可以使用符合IEEE 1149.1测试标准并在单个芯片上配置。 该芯片可以通过PC或工作站进行远程控制，以产生刺激并收集响应数据，以充分测试与测试芯片脚印匹配的IC。 指定的技术在单个芯片上使用具有附加逻辑的IEEE测试标准，允许在IC的速度测试功能测试。 测试芯片可以通过四（4）个通道测试访问端口连接到PC或工作站。 通过从PC或工作站远程控制测试芯片，可以产生刺激和响应数据，以完全测试具有与测试芯片的IC匹配的脚印的任何集成电路。 在一个实施例中，测试芯片安装在探针卡上用于晶片的速度功能测试。 在另一个实施例中，将测试芯片放置在插座或适配器中以进行速度封装水平测试。 在另一个实施例中，测试芯片夹在待测器件（DUT）和安装有DUT的PCB之间用于速度板测试。

公开(公告)号：US5301199A

公开(公告)日：1994-04-05

申请号：US991535

申请日：1992-12-15

Applicant: Takeshi Ikenaga ,  Jun-ichi Takahashi

Inventor： Takeshi Ikenaga ,  Jun-ichi Takahashi

IPC: G01R31/3185 ,  H04B17/00

CPC classification number: G01R31/3185 ,  G06F2201/83

Abstract: A built-in self test circuit includes a pattern generator, a functional block subjected to a self test on the basis of an output from the pattern generator, a space compressor for compressing a test result of the functional block, and a comparator for comparing an output from the space compressor with an expected value and outputting a comparison result. The functional block has O (positive integer) inputs and M (positive integer) outputs. The pattern generator is constituted by a linear feedback shift register, having an output bit width P (P=O/N) which is 1/N of the inputs O of the functional block, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from the linear feedback shift register in units of N outputs and outputting, to the functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from the linear feedback shift register every P bits. The space compressor has a function of spatially compressing the M outputs from the functional block into L outputs (positive integer and M>L). The pattern generator, the functional block, the space compressor, and the comparator are built into a semiconductor chip into which other functional elements are built.

Abstract translation: 内置的自检电路包括：图案发生器，基于来自图案生成器的输出进行自检的功能块，用于压缩功能块的测试结果的空间压缩器，以及比较器 从空间压缩机输出预期值并输出比较结果。 功能块有O（正整数）输入和M（正整数）输出。 图形发生器由线性反馈移位寄存器构成，具有作为功能块的输入O的1 / N的输出位宽度P（P = O / N），用于生成伪随机模式和迭代伪随机模式输出 单元，用于以N个输出为单位分配来自线性反馈移位寄存器的输出，并向功能块输出具有从线性输出的伪随机模式的迭代O位宽度（O = P * N）的迭代伪随机模式输出 反馈移位寄存器每P位。 空间压缩器具有将功能块的M个输出空间压缩为L个输出（正整数和M> L）的功能。 图案发生器，功能块，空间压缩器和比较器内置在其中构建其它功能元件的半导体芯片中。

公开(公告)号：US5274817A

公开(公告)日：1993-12-28

申请号：US812445

申请日：1991-12-23

Applicant: Alan L. Stahl

Inventor： Alan L. Stahl

IPC: G06F9/38 ,  G06F9/42 ,  G06F11/28 ,  G06F7/00 ,  G06F15/00

CPC classification number: G06F9/3806 ,  G06F11/28 ,  G06F9/30054 ,  G06F9/4426 ,  G06F2201/83

Abstract: A method is provided for executing a subroutine in a computer which includes a memory and a stack. The memory has a plurality of sequentially ordered memory address locations referenced by respective address codes. The subroutine is stored in a preselected range of memory locations. The method includes storing a signature word on the stack, the signature word corresponding to an entry address code in memory for the subroutine; storing a return address on the stack, the return address code corresponding to a memory location where control is to be passed after execution of the subroutine; passing control to the subroutine entry address; executing the subroutine; comparing the signature word stored on the stack with the subroutine entry address code; passing control to the return address if the compared values are equal; and executing a software interrupt if the compared values are not equal.

Abstract translation: 提供一种用于在包括存储器和堆栈的计算机中执行子程序的方法。 存储器具有由相应地址码引用的多个顺序排列的存储器地址位置。 子程序存储在存储器位置的预选范围内。 所述方法包括：在所述堆栈中存储签名字，所述签名字对应于所述子例程的存储器中的条目地址码; 在所述堆栈上存储返回地址，所述返回地址代码对应于在执行所述子程序之后要传递控制的存储器位置; 将控制传递给子程序入口地址; 执行子程序; 将堆栈中存储的签名字与子程序入口地址代码进行比较; 如果比较值相等，则将控制传递给返回地址; 并且如果所比较的值不相等则执行软件中断。