公开(公告)号：US20240220382A1

公开(公告)日：2024-07-04

申请号：US18400521

申请日：2023-12-29

Applicant: TDI Novus, Inc.

Inventor： Avinash Srinivasan

IPC: G06F11/28

CPC classification number: G06F11/28

Abstract: An anomaly monitoring system for a cyber-physical environment having at least one programmable logic controller (PLC) and a monitored component, the monitoring system having a human machine interface, a separate controller with at least a processor and associated memory, and providing a communication network for electronic communication between components of the cyber-physical environment, the anomaly monitoring system providing at least one plugin module to monitor the performance of the component and the PLC, as provided through the communication network through a PLC data collection module, the plugin comparing the data from the PLC data collection module to a model of learned behavior patterns, and thereby classify reviewed data as being normal or anomaly events.

公开(公告)号：US20240160548A1

公开(公告)日：2024-05-16

申请号：US18550136

申请日：2022-01-20

Applicant: SONY GROUP CORPORATION

Inventor： KAORU AMEMIYA ,  ITARU SHIMIZU ,  SUGURU AOKI ,  YOSHIYUKI KOBAYASHI

IPC: G06F11/28

CPC classification number: G06F11/28

Abstract: The present technology relates to an information processing system, an information processing method, and a program that make it possible to determine execution of learning, without relying on external instruction inputs. The information processing system determines an action on the basis of environmental information and a learning model obtained through learning based on an evaluation function for evaluating an action. The information processing system includes an error detection unit configured to determine a magnitude of a differential between the environmental information that has been newly input or the evaluation function that has been newly input and the environmental information that has existed or the evaluation function that has existed and a learning unit configured to update, depending on the magnitude of the differential, the learning model on the basis of the environmental information that has been newly input or the evaluation function that has been newly input and an amount of reward obtained for an action through the evaluation. The present technology can be applied to information processing systems.

公开(公告)号：US20240061759A1

公开(公告)日：2024-02-22

申请号：US17754561

申请日：2021-07-06

Applicant: Beijing Baidu Netcom Science and Technology Co., Ltd.

Inventor： Chen Ma

IPC: G06F11/28

CPC classification number: G06F11/28

Abstract: An automatic test method and apparatus, an electronic device, and a storage medium are provided, which relate to the fields of the automatic test, the voice testing, the voice effect acceptance check, etc. The method includes: receiving a test task initiated by a visualization front-end; issuing the test task to a plurality of clients deployed; and scheduling execution of the test task for the plurality of clients, and feeding back obtained task execution results to the visualization front-end.

公开(公告)号：US11853151B1

公开(公告)日：2023-12-26

申请号：US18165925

申请日：2023-02-07

Applicant: Realtek Semiconductor Corporation

Inventor： Siwei Jiang ,  Kun-Hsuan Wu ,  Hong Zhang ,  Shuyu Deng

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/28

CPC classification number: G06F11/079 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/28

Abstract: An embedded device detection method, comprising the following steps: executing a task by an embedded device, wherein the task comprises multiple functions; when an abnormal interruption occurs to the task, obtaining a stack pointer and a program counter corresponding to the abnormal interruption by a detection device, wherein the program counter is configured to record a memory address in use when the abnormal interruption occurs to the task; obtaining a stack space corresponding to a first target function being executed according to the program counter when the abnormal interruption occurs to the task; finding out a second target function before the first target function is executed according to the stack pointer and the stack space; and correcting the task according to the second target function.

公开(公告)号：US20190205528A1

公开(公告)日：2019-07-04

申请号：US16235731

申请日：2018-12-28

Applicant: GUARDSQUARE NV

Inventor： Sander Bogaert

IPC: G06F21/52 ,  G06F21/12 ,  G06F21/64 ,  G06F11/28 ,  G06F8/75 ,  G06F9/30 ,  G06F9/448

CPC classification number: G06F11/28

Abstract: An automated application verification module is provided to identify one or more functions of a software application. There is added, for at least one of the identified functions, a verification prologue at the entry point of the function which does not alter the control flow of the original set of instructions of the function and/or does not change the semantics of the function when the verification prologue is executed in its entirety. There is added at least one corresponding verification prologue check to the software application, such that the verification prologue check is configured to automatically check the integrity of the corresponding verification prologue during execution of the software application.

公开(公告)号：US20190163446A1

公开(公告)日：2019-05-30

申请号：US15861021

申请日：2018-01-03

Applicant: The MathWorks, Inc.

Inventor： Jean Yves Brunel

IPC: G06F8/10 ,  G06F8/35 ,  G06F11/36

CPC classification number: G06F8/10 ,  G06F8/35 ,  G06F8/42 ,  G06F8/43 ,  G06F8/74 ,  G06F11/28 ,  G06F11/3604 ,  G06F11/3616

Abstract: A code-proving system is adapted to analyze implementation code for compliance with a at least a specified model. The implementation code can be code that is used to provide control or semi-automated control of a complex electromechanical system, such as an automobile. The specified model may be written to comply with a meta-model such as the software architecture specification known as Automotive Open System Architecture (AUTOSAR).

公开(公告)号：US20180260564A1

公开(公告)日：2018-09-13

申请号：US15909253

申请日：2018-03-01

Applicant: SECURE-IC SAS

Inventor： Thibault PORTEBOEUF

IPC: G06F21/56 ,  G06F21/71 ,  H04L29/06 ,  H04L9/08 ,  H04L9/32 ,  G06F13/28

CPC classification number: G06F21/566 ,  G06F11/28 ,  G06F11/3636 ,  G06F13/28 ,  G06F21/52 ,  G06F21/54 ,  G06F21/71 ,  H04L9/0825 ,  H04L9/0866 ,  H04L9/3242 ,  H04L63/123

Abstract: There is disclosed a circuit for monitoring the security of a processor, wherein the circuit is configured to access a memory configured to store execution context data of a software program executed by the processor; to determine one or more signatures from said execution context data; and to compare said signatures with predefined signatures to monitor the security of the processor (110). Developments describe that context data can comprise control flow data, that a signature can comprise a hash value or a similarity signature, or that the integrity of signatures can be verified for example by using a secret key (e.g. obtained by random, or by using a physically unclonable function). Further developments describe various controls or retroactions on the processor, as well as various countermeasures if cyber attacks are determined.

公开(公告)号：US20180189165A1

公开(公告)日：2018-07-05

申请号：US15740242

申请日：2015-10-26

Applicant: HITACHI, LTD.

Inventor： Hiroyuki YAMADA ,  Hirokazu TANIYAMA ,  Masashi NAKAOKA ,  Masatoshi YOSHIDA ,  Yuki SHIMIZU

IPC: G06F11/36 ,  G06F11/28 ,  G06F9/445

CPC classification number: G06F11/362 ,  G06F9/44536 ,  G06F11/00 ,  G06F11/28 ,  G06F11/3664

Abstract: In testing a component-set whole process which includes a plurality of components and in which the order of execution of the plurality of components is defined, a computer system exports, to a storage resource, an input package for at least one component to be executed. Each of the plurality of components is a module of a significant process as a set of one or more processing steps and independent of any other components. Each input package includes an input value of a component that corresponds to the input package. The computer system imports an exported input package of a component to be debugged into the component to be debugged in order to execute the component to be debugged, without executing a component the order of which precedes the order N (where N is a natural number) of the component to be debugged.

公开(公告)号：US20180018250A1

公开(公告)日：2018-01-18

申请号：US15724902

申请日：2017-10-04

Applicant: International Business Machines Corporation

Inventor： Dean G. Bair ,  Rebecca M. Gott ,  Edward J. Kaminski, JR. ,  William J. Lewis ,  Chakrapani Rayadurgam

IPC: G06F11/28 ,  G11C29/44 ,  G11C29/38 ,  G06F11/27 ,  G06F11/07 ,  G06F11/263 ,  G06F11/25 ,  G11C29/54 ,  G06F11/273

CPC classification number: G06F11/28 ,  G06F11/073 ,  G06F11/25 ,  G06F11/261 ,  G06F11/263 ,  G06F11/2635 ,  G06F11/27 ,  G06F11/2733 ,  G11C29/38 ,  G11C29/44 ,  G11C29/54

Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.

公开(公告)号：US20170344503A1

公开(公告)日：2017-11-30

申请号：US15680755

申请日：2017-08-18

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F13/364 ,  G06F13/36 ,  G06F11/30 ,  G06F11/28 ,  G06F9/46 ,  G06F13/42 ,  G06F5/00

CPC classification number: G06F13/364 ,  G06F5/00 ,  G06F9/467 ,  G06F11/28 ,  G06F11/30 ,  G06F13/36 ,  G06F13/4282

Abstract: Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.