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    Firmware mechanism for correcting soft errors
    51.
    发明授权
    Firmware mechanism for correcting soft errors 有权
    用于纠正软错误的固件机制

    公开(公告)号：US06625749B1

    公开(公告)日：2003-09-23

    申请号：US09469963

    申请日：1999-12-21

    Applicant: Nhon Quach

    Inventor： Nhon Quach

    IPC: G06F1100

    CPC classification number: G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F2201/845

    Abstract: A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.

    Abstract translation: 计算机系统包括具有双执行核心的处理器和存储错误恢复例程的非易失性存储器。 当处理器处于冗余执行模式时，处理器的执行核心以锁定步骤运行，并且当处理器处于分离执行模式时，它们独立运行。 当处理器在冗余执行模式下运行时检测到软错误时，会调用错误恢复程序。 错误恢复程序将处理器切换到分割执行模式。 在分离模式下，每个执行核心将未处理的处理器状态数据保存到指定的存储器位置，并使用来自其他执行核心的相应处理器状态数据更新任何损坏的数据。 错误恢复程序将处理器返回到冗余模式，用恢复的处理器状态数据初始化每个执行核心，并将处理器的控制权返回到检测到软错误时执行的程序线程。

    Multi-processor system bridge
    52.
    发明授权
    Multi-processor system bridge 失效
    多处理器系统桥

    公开(公告)号：US06173351B2

    公开(公告)日：2001-01-09

    申请号：US09097497

    申请日：1998-06-15

    Applicant: Paul J. Garnett ,  Stephen Rowlinson ,  Femi A. Oyelakin

    Inventor： Paul J. Garnett ,  Stephen Rowlinson ,  Femi A. Oyelakin

    IPC: G06F1338

    CPC classification number: G06F11/1641 ,  G06F11/1658 ,  G06F11/1683 ,  G06F13/4036 ,  G06F2201/845

    Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

    Abstract translation: 用于多处理器系统的桥提供到第一处理集合的I / O总线，第二处理集合的I / O总线和设备总线的接口。 桥接控制机构在第一和第二处理组之间仲裁以便以第一，分离模式访问彼此的I / O总线和设备总线，并且监视第二和第二处理组的锁步操作， 组合，模式。 在检测组合模式下的锁步错误时，桥接器将转移到错误模式。 桥接控制机制在错误模式中缓冲写入缓冲区中的写入访问，等待解决错误。

    Protocol for read write transfers via switching logic by transmitting and retransmitting an address
    53.
    发明授权
    Protocol for read write transfers via switching logic by transmitting and retransmitting an address 失效
    通过发送和重新发送地址通过切换逻辑进行读写操作的协议

    公开(公告)号：US5163138A

    公开(公告)日：1992-11-10

    申请号：US388029

    申请日：1989-08-01

    Applicant: Ajai Thirumalai

    Inventor： Ajai Thirumalai

    IPC: G06F11/20 ,  G06F11/00 ,  G06F15/17

    CPC classification number: G06F11/165 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/2017 ,  G06F15/17 ,  G06F2201/845

    Abstract: A process for transferring information including a source or destination address between two nodes in a network via data switching logic. The switching logic must decode commands and addresses in order to adopt the proper configuration so that the commands and addresses can be forwarded from one system resource to another system resource. A read or write address is transmitted to the switching logic and decoded in order to configure the switching logic. The same read or write address is then retransmitted to the switching logic for forwarding to the appropriate system resource. As a result, there is no need for extra storage logic in order to retain read and write addresses while the switching logic is being configured.

    Program controlled data processing system
    54.
    发明授权
    Program controlled data processing system 失效
    程序控制数据处理系统

    公开(公告)号：US3651480A

    公开(公告)日：1972-03-21

    申请号：US3651480D

    申请日：1967-11-24

    Applicant: BELL TELEPHONE LABOR INC

    Inventor： DOWNING RANDALL W ,  NOWAK JOHN S ,  TAYLOR FRANK F ,  ULRICH WERNER

    IPC: G06F11/16 ,  H04Q3/545 ,  G06F15/16

    CPC classification number: G06F11/1654 ,  G06F11/1633 ,  G06F11/165 ,  G06F2201/845 ,  H04Q3/5455 ,  H04Q3/54591

    Abstract: A program controlled data processor system which employs functionally equivalent first and second control units on a mutually exclusive basis to control an input-output system. The processor system comprises a plurality of independent memory units and communication between the control means and the independent memory units is by way of communication paths which may be selectively associated with any of the memory units and with either of the control means. The processor arrangement includes means for insuring that the two control means simultaneously carry out identical work functions.

    Abstract translation: 一种程序控制的数据处理器系统，其在相互排斥的基础上采用功能上等效的第一和第二控制单元来控制输入 - 输出系统。 处理器系统包括多个独立的存储器单元，并且控制装置和独立存储器单元之间的通信是通过可以选择性地与任何存储器单元和控制装置中的任何一个相关联的通信路径。 处理器装置包括用于确保两个控制装置同时执行相同功能的装置。

    Package On Package Memory Interface and Configuration With Error Code Correction
    58.
    发明申请
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开

    公开(公告)号：US20180364051A1

    公开(公告)日：2018-12-20

    申请号：US16114419

    申请日：2018-08-28

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Moody

    IPC: G01C21/20

    CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

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