公开(公告)号：US08898891B2

公开(公告)日：2014-12-02

申请号：US12961610

申请日：2010-12-07

Applicant: Joel R. Goergen ,  Yi Zheng

Inventor： Joel R. Goergen ,  Yi Zheng

IPC: H05K3/42 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0216 ,  B32B2305/076 ,  B32B2309/08 ,  B32B2457/08 ,  H01P3/081 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/0091 ,  H05K3/46 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09745 ,  H05K2201/098 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract translation: 公开了电路板及其制造方法。 电路板使用形成为包括纵向通道的导体承载高速信号。 通道增加了导体的表面积，从而增强了导体承载高速信号的能力。 在至少一些实施例中，通道内的介电常数和通道之外的介质常数之间也存在不连续性，这被认为可减少信号损耗。

公开(公告)号：US08853546B2

公开(公告)日：2014-10-07

申请号：US12837543

申请日：2010-07-16

Applicant: Daisuke Yamauchi ,  Tetsuya Oosawa ,  Mitsuru Honjo ,  Masami Inoue

Inventor： Daisuke Yamauchi ,  Tetsuya Oosawa ,  Mitsuru Honjo ,  Masami Inoue

IPC: H05K1/00 ,  H05K3/36 ,  H05K3/24 ,  H05K1/05 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/056 ,  C25D7/00 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/10977 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: A base insulating layer is formed on a suspension body. A lead wire for plating and a wiring trace are integrally formed on the base insulating layer. A cover insulating layer is formed on the base insulating layer to cover the lead wire for plating and the wiring trace. A thickness of a portion of the cover insulating layer above a region of the base insulating layer in which the lead wire for plating is formed is set smaller than the thickness of a portion of the cover insulating layer above other regions of the base insulating layer.

Abstract translation: 基体绝缘层形成在悬架体上。 在基底绝缘层上一体地形成电镀用引线和布线迹线。 覆盖绝缘层形成在基底绝缘层上以覆盖电镀用引线和布线迹线。 在形成有电镀用引线的基极绝缘层的区域的上方的覆盖绝缘层的一部分的厚度设定为小于基底绝缘层的其它区域以上的覆盖绝缘层的一部分的厚度。

公开(公告)号：US20140251663A1

公开(公告)日：2014-09-11

申请号：US14205337

申请日：2014-03-11

Applicant: Sanmina Corporation

Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, Jr.

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/036 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/0713 ,  H05K2203/0723

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract translation: 提供了具有选择性地定位在第一介电层中的第一电介质层和第一电镀抗蚀剂的多层印刷电路板。 可以将第二电镀抗蚀剂选择性地定位在第一电介质层或第二电介质层中，第二电镀抗蚀剂与第一电镀抗蚀剂分离。 通孔延伸穿过第一电介质层，第一电镀抗蚀剂和第二电镀抗蚀剂。 除了沿第一电镀抗蚀剂和第二电镀抗蚀剂之间的长度之外，通孔的内表面镀有导电材料。 这形成了具有与第二通孔段电隔离的第一通路段的分隔电镀通孔。

公开(公告)号：US08823145B2

公开(公告)日：2014-09-02

申请号：US12331734

申请日：2008-12-10

Applicant: Kyung Ho Shin

Inventor： Kyung Ho Shin

IPC: H01L23/48 ,  H01L23/495 ,  H01L29/06

CPC classification number: H05K1/0206 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2224/49113 ,  H01L2924/13062 ,  H01L2924/13091 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a multilayer board and a light-emitting module having the same. The light-emitting module comprises a light-emitting diode chip and a multilayer board. The multilayer board is electrically connected to the light-emitting diode chip and comprises a nonconductive heat sink via and a thin copper layer.

Abstract translation: 提供了一种多层板和具有该多层板的发光模块。 发光模块包括发光二极管芯片和多层板。 多层板电连接到发光二极管芯片，并包括非导电散热片和薄铜层。

公开(公告)号：US20140240932A1

公开(公告)日：2014-08-28

申请号：US13843873

申请日：2013-03-15

Applicant: MC10, INC.

Inventor： Yung-Yu Hsu

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0283 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/118 ,  H05K1/147 ,  H05K1/148 ,  H05K1/189 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/09245 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2201/2009

Abstract: Buffer structures are provided that can be used to reduce a strain in a conformable electronic system that includes compliant components in electrical communication with more rigid device components. The buffer structures are disposed on, or at least partially embedded in, the conformable electronic system such that the buffer structures overlap with at least a portion of a junction region between a compliant component and a more rigid device component. The buffer structure can have a higher value of Young's modulus than an encapsulant of the conformable electronic system.

Abstract translation: 提供缓冲结构，其可以用于减少适应电子系统中的应变，其包括与更刚性的装置部件电连通的顺应部件。 缓冲结构设置在适配电子系统上或至少部分嵌入适配电子系统中，使得缓冲结构与柔顺部件和更刚性的器件部件之间的连接区域的至少一部分重叠。 缓冲结构可以具有比适形电子系统的密封剂更高的杨氏模量值。

公开(公告)号：US20140240062A1

公开(公告)日：2014-08-28

申请号：US13854948

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Gerd Schuppener ,  Robert Floyd Payne

IPC: H01P3/16

CPC classification number: H01P3/16 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01P1/04 ,  H01P3/121 ,  H01Q13/00 ,  H05K1/0239 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09618 ,  H05K2201/10098 ,  Y10T29/49826 ,  Y10T29/49908

Abstract: A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG

Abstract translation: 电介质波导（DWG）具有第一介电常数值的介质芯构件。 围绕介电芯构件的包层具有低于第一介电常数的第二介电常数值。 DWG的配合端配置成与具有匹配的非平面形状配合端的第二DWG配合。 可变形材料设置在DWG的配合端的表面上，使得当与第二DWG配合时，可变形材料填充DWG的配合端和第二DWG之间的间隙区域

公开(公告)号：US20140206240A1

公开(公告)日：2014-07-24

申请号：US13802844

申请日：2013-03-14

Applicant: COMMSCOPE, INC. OF NORTH CAROLINA

Inventor： Richard A. Schumacher ,  Ryan E. Enge ,  Wayne D. Larsen ,  Bryan S. Moffitt ,  Julian Pharney

IPC: H01R13/6461

CPC classification number: H01R13/6473 ,  H01R13/6461 ,  H01R13/6466 ,  H01R24/64 ,  H05K1/0219 ,  H05K1/0228 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/117 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/1034 ,  H05K2201/10356

Abstract: Communications connectors include a housing and a printed circuit board that is at least partially mounted in the housing that has a plurality of conductive paths that are arranged in pairs to form a plurality of differential transmission lines. These connectors further include a plurality of contacts, each of which is electrically connected to a respective one of the conductive paths of the printed circuit board. The printed circuit board further includes at least a first floating image plane that is located between a top surface and a bottom surface thereof, the floating image plane being electrically isolated from the plurality of conductive paths.

Abstract translation: 通信连接器包括壳体和印刷电路板，其至少部分地安装在壳体中，该壳体具有成对布置成多个导电路径以形成多个差动传输线。 这些连接器还包括多个触点，每个触点电连接到印刷电路板的相应一个导电路径。 印刷电路板还包括位于其顶表面和底表面之间的至少第一浮动图像平面，浮动图像平面与多个导电路径电隔离。

公开(公告)号：US20140183750A1

公开(公告)日：2014-07-03

申请号：US14188093

申请日：2014-02-24

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Scott Smith ,  Elizabeth Ann Burke

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2021/60 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/144 ,  H05K1/185 ,  H05K1/189 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/467 ,  H05K3/4673 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/09136 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material and a die is positioned within the die opening of the initial laminate flex layer and onto the adhesive material. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer by way of an adhesive material and the adhesive materials are then cured. Vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die.

Abstract translation: 形成掩埋模具模块的方法包括提供初始层叠柔性层并通过初始层压柔性层形成模具开口。 第一未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第一表面，并且模具定位在初始层压柔性层的模具开口内并粘附到粘合剂材料上。 第二未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第二表面上，然后固化粘合剂材料。 在第一和第二未切割的层叠柔性层中和第二未切割的层叠柔性层上形成通孔和金属互连，其中每个金属互连件延伸通过相应的通孔，并且直接金属化到初始层压柔性层上的金属互连或模具上的管芯焊盘 。

公开(公告)号：US08763241B2

公开(公告)日：2014-07-01

申请号：US13239487

申请日：2011-09-22

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K3/30

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed circuit board including providing a first resin substrate having a resin plate and a circuit pattern formed on a surface of the resin plate, providing a second resin substrate having a resin plate and an accommodation portion formed in the resin plate of the second substrate, connecting an electrode of a capacitor to the circuit pattern of the first substrate with a bonding material such that the capacitor is mounted to the first substrate, attaching the second substrate to the resin substrate through a bonding resin layer such that the capacitor on the first substrate is accommodated in the accommodation portion of the second substrate, and forming a via hole in the first substrate such that the via hole is electrically connected to the electrode of the capacitor in the accommodation portion of the second substrate.

Abstract translation: 一种制造印刷电路板的方法，包括提供具有树脂板的第一树脂基板和形成在树脂板的表面上的电路图案，提供具有树脂板和形成在树脂板中的容纳部分的第二树脂基板 第二基板，利用接合材料将电容器的电极连接到第一基板的电路图案，使得电容器安装到第一基板，通过接合树脂层将第二基板附着到树脂基板，使得电容器 在第一基板上容纳在第二基板的容纳部分中，并且在第一基板中形成通孔，使得通孔与第二基板的容纳部分中的电容器的电极电连接。

公开(公告)号：US20140146499A1

公开(公告)日：2014-05-29

申请号：US14092771

申请日：2013-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjea Jang ,  Jaewoong Kim ,  Taewoo Kim

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10734

Abstract: A printed circuit board (PCB) having a decoupling capacitor includes: a PCB including a power supply layer, ground layer, and first decoupling capacitor; a package mounted at a surface of the PCB, wherein the first decoupling capacitor is embedded in a via hole of the PCB, and a first electrode of the first decoupling capacitor is connected to one of power supply pins of the package, and a second electrode of the first decoupling capacitor is connected to the ground layer.

Abstract translation: 具有去耦电容器的印刷电路板（PCB）包括：包括电源层，接地层和第一去耦电容器的PCB; 封装，其安装在所述PCB的表面处，其中所述第一去耦电容器嵌入在所述PCB的通孔中，并且所述第一去耦电容器的第一电极连接到所述封装的电源引脚之一，并且第二电极 的第一个去耦电容连接到接地层。