公开(公告)号：US20250004530A1

公开(公告)日：2025-01-02

申请号：US18345940

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregg Donley

IPC: G06F9/30

Abstract: The disclosed device includes multiple data elements each configured to send a bit of a bit sequence by toggling at most half of a number of bits from a previously sent bit sequence. The bit sequence can first be biased and then XORed with the previously sent bit sequence. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250001312A1

公开(公告)日：2025-01-02

申请号：US18346096

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Le Zhang ,  Wei Liang ,  Ilia Blank ,  Patrick Pak Kin Fok ,  Eleftherios Makedon ,  Amir Alam ,  Sebastian Borkowski ,  Goverdhan Aligeti

IPC: A63F13/77 ,  A63F13/335 ,  A63F13/35

Abstract: Systems and methods for crowdsourcing cloud application execution are described. An application system receives, from a client device, a first request to initiate an application session. The application system identifies a host device to fulfill the first request. The application system then initiates execution of the application session on the host device and generates, for the client device, a plurality of controls to control the application session executing on the host device. The host device is incentivized for each application session hosted.

公开(公告)号：US12182611B2

公开(公告)日：2024-12-31

申请号：US18145457

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Philip Ng ,  Anil Kumar

IPC: G06F9/48 ,  G06F9/30 ,  G06F11/07

Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.

公开(公告)号：US12176065B2

公开(公告)日：2024-12-24

申请号：US17849197

申请日：2022-06-24

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Xuan Chen ,  Chih-Hua Hsu ,  Pradeep Jayaraman ,  Abdussalam Aburwein

IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10 ,  G11C8/18

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

公开(公告)号：US12174771B2

公开(公告)日：2024-12-24

申请号：US18392072

申请日：2023-12-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yulei Shen ,  Tyrone Tung Huang ,  Chen-Kuan Hong

IPC: G06F13/40 ,  G06F13/20 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

公开(公告)号：US12169430B2

公开(公告)日：2024-12-17

申请号：US17824844

申请日：2022-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Raul Gutierrez

IPC: G06F1/3234 ,  G06F13/10

Abstract: Systems and methods are disclosed for reducing power consumed by capturing data from an I/O device. Techniques disclosed include receiving descriptors, by a controller of an I/O host of a system, including information associated with respective data chunks to be captured from an I/O device buffer of the I/O device. Techniques disclosed further include capturing, based on the descriptors, the data chunks. The capturing comprises pulling the data chunks from the I/O device buffer at a pulling rate, where the data chunks are transferred to a local buffer of the I/O host, and pushing segments of the pulled data chunks from the local buffer, where each segment is transferred to a data buffer of the system after a respective target time that precedes a time at which the data chunks in the segment are to be processed by an application executing on the system.

公开(公告)号：US20240412445A1

公开(公告)日：2024-12-12

申请号：US18332562

申请日：2023-06-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： David William John Pankratz ,  David Ronald Oldcorn

IPC: G06T15/06 ,  G06T15/00

Abstract: A technique for performing ray tracing operations is provided. The technique includes, traversing through a bounding volume hierarchy for a ray to arrive at a well-fit bounding volume that is associated with first node, wherein the first node is one of a traversal node or a procedural node, and wherein the well-fit bounding volume comprises geometry other than a single axis-aligned bounding box for the first node; evaluating the ray for intersection with the well-fit bounding volume; determining whether to execute a first shader program associated with the first node based on the evaluating, wherein the first shader program comprises a traversal shader program or a procedural shader program; and executing or not executing the first shader program based on the determining.

公开(公告)号：US20240411692A1

公开(公告)日：2024-12-12

申请号：US18332112

申请日：2023-06-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Hsiuwei Loh ,  Joseph Lee Greathouse ,  William Louie Walker ,  Paul James Moyer

IPC: G06F12/0802

Abstract: Cache replacement policies are described. In accordance with the described techniques, a request for data is received and a cache replacement policy controls how a controller responds to the request. The cache replacement policy assigns each cacheline a priority value, which indicates whether the cacheline should be preserved relative to other cachelines, in response to the request being a cache miss that necessitates eviction of at least one cacheline. The cache replacement policy decrements priority values until at least one cacheline achieves a minimum priority value, at which point a cacheline is evicted. The cache replacement policy designates certain cachelines as protected, either via a separate protected indicator or via the cacheline's priority value, which causes unprotected cachelines to be selected for eviction while favoring preservation of protected cachelines in the cache.

公开(公告)号：US12165700B2

公开(公告)日：2024-12-10

申请号：US17488519

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu ,  Keith A. Kasprak

IPC: G11C11/419 ,  G11C11/418

Abstract: A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

公开(公告)号：US12165252B2

公开(公告)日：2024-12-10

申请号：US18480466

申请日：2023-10-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind N. Nemlekar ,  Maxim V. Kazakov ,  Prerit Dak

IPC: G06T15/00 ,  G06F9/54 ,  G06T15/80

Abstract: Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such completion and proceeding to a subsequent kernel dispatch packet.