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61.发明公开公开(公告)号：US20230363136A1
公开(公告)日：2023-11-09
申请号：US17931888
申请日：2022-09-13
Inventor： Deyuan XIAO , Yong YU , Guangsu SHAO
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814 , H01L27/10852
Abstract: A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.
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公开(公告)号：US20230200045A1
公开(公告)日：2023-06-22
申请号：US17934489
申请日：2022-09-22
Inventor： Guangsu SHAO , Deyuan XIAO , Yunsong QIU , Minmin WU
IPC: H10B12/00
CPC classification number: H10B12/053 , H10B12/34 , H10B12/482 , H10B12/488
Abstract: A semiconductor device includes a substrate. A method includes the following operations. Multiple first trenches extending in a first direction are formed in the substrate. Multiple second trenches extending in a second direction are formed in the substrate in which the first trenches are formed. The first direction is perpendicular to the second direction. A first depth of a first trench is equal to a second depth of a second trench. A first insulating layer, a conducting layer and a second insulating layer are formed in sequence in the first and second trenches. The conducting layer in the first trench is separated on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction. Word lines extending in the second direction are formed on the conducting layer in the first and second trenches.
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公开(公告)号：US20230172074A1
公开(公告)日：2023-06-01
申请号：US17847186
申请日：2022-06-23
Inventor： Xiaoguang WANG , Huihui LI , Qiang ZHANG , Shan WANG , Minmin WU
Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The fabricating method includes: providing a substrate including an array region and a peripheral region; and forming, on the substrate, a first mask layer covering the array region and the peripheral region, the first mask layer having a first device structure pattern directly facing the array region and a second device structure pattern directly facing the peripheral region. Through the method for fabricating a semiconductor structure, the first mask layer having the first device structure pattern and the second device structure pattern is formed on the substrate, and then the substrate is etched by using the first device structure pattern and the second device structure pattern as mask layer to synchronously form a peripheral region structure and an array region structure on the substrate.
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公开(公告)号：US20230171970A1
公开(公告)日：2023-06-01
申请号：US17827808
申请日：2022-05-30
Inventor： Xiaoguang WANG , Huihui LI , Wei CHANG , Kanyu CAO
IPC: H01L27/105
CPC classification number: H01L27/1052
Abstract: Embodiment provides a semiconductor structure and a fabrication method thereof, and relates to the field of semiconductor technology. The method includes: providing a substrate having an array region including a first region and a second region arranged adjacently; and forming a first memory in the first region and forming a second memory in the second region by means of a same fabrication process, the fabrication process being a process configured for fabricating the first memory.
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公开(公告)号：US20230171942A1
公开(公告)日：2023-06-01
申请号：US17818509
申请日：2022-08-09
Inventor： Deyuan XIAO , Yong YU , Guangsu SHAO
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814 , H01L27/10885
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars on the substrate, where each of the active pillars includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.
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Patent Agency Ranking
公开(公告)号：US20230171941A1
公开(公告)日：2023-06-01
申请号：US17817750
申请日：2022-08-05
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814 , H01L27/10885
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming active pillars arranged at intervals on the substrate, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially along a first direction; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a word line structure on a sidewall of the gate oxide layer, the word line structure includes a first word line structure and a second word line structure that are made of different materials, and the first word line structure is connected to the sidewall of the gate oxide layer, and partially covers the second word line structure.
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公开(公告)号：US20230171938A1
公开(公告)日：2023-06-01
申请号：US17817405
申请日：2022-08-04
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108 , H01L29/78
CPC classification number: H01L27/10864 , H01L27/10891 , H01L27/10885 , H01L29/7827
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array on the substrate, where the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially, and along a second direction, a cross-sectional area of the second segment is smaller than those of the first segment and the third segment; forming a gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a gate dielectric layer on the gate oxide layer, where the gate dielectric layer is shorter than the gate oxide layer, and is close to the third segment.
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公开(公告)号：US20230170224A1
公开(公告)日：2023-06-01
申请号：US17826177
申请日：2022-05-27
Inventor： Xiaoguang WANG , Huihui LI , Qiang ZHANG , Shan WANG , Minmin WU
IPC: H01L21/308 , H01L21/033 , H01L27/108
CPC classification number: H01L21/3086 , H01L21/0337 , H01L27/10894 , H01L21/3081
Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first device structure pattern on the first mask layer, and then forming a second device structure pattern on the first mask layer; and etching the substrate by using the first device structure pattern and the second device structure pattern as mask layer to form a peripheral region structure and an array region structure synchronously on the substrate. Technological processes are simplified, fabrication difficulties are reduced, and production efficiency is improved.
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公开(公告)号：US20230068461A1
公开(公告)日：2023-03-02
申请号：US17812549
申请日：2022-07-14
Inventor： Xiaoguang Wang , Dinggui Zeng , Huihui Li , Kanyu Cao
IPC: H01L43/08 , H01L27/22 , H01L43/02 , H01L43/12 , H01L23/528 , H01L29/423 , H01L29/786
Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.
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公开(公告)号：US20230067509A1
公开(公告)日：2023-03-02
申请号：US17808382
申请日：2022-06-23
Inventor： Xiaoguang Wang , Dinggui Zeng , Huihui Li , Kanyu Cao
IPC: H01L27/22 , H01L29/786 , H01L43/12 , H01L29/66
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate. A plurality of vertical transistors arranged in an aligned manner are formed on the substrate, wherein a channel material of the vertical transistor includes an oxide semiconductor. A plurality of staggered contact pads connected to upper ends of the vertical transistors are formed on the vertical transistors, wherein a single contact pad is connected to the upper ends of an even number of vertical transistors. A magnetic tunnel junction is formed on the contact pad.
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