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    3D STACKED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC EQUIPMENT
    2.
    发明申请
    3D STACKED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC EQUIPMENT 有权

    公开(公告)号：US20250048615A1

    公开(公告)日：2025-02-06

    申请号：US18692912

    申请日：2023-06-08

    Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Xuezheng Ai ,  Xiangsheng Wang ,  Guilei Wang ,  Jin Dai ,  Chao Zhao ,  Wenhua Gui

    IPC: H10B12/00

    Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

    Method for forming capacitor, capacitor and semiconductor device
    5.
    发明授权
    Method for forming capacitor, capacitor and semiconductor device 有权

    公开(公告)号：US12041763B2

    公开(公告)日：2024-07-16

    申请号：US17848895

    申请日：2022-06-24

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Guangsu Shao ,  Mengkang Yu ,  Xingsong Su

    IPC: H01L27/108 ,  H10B12/00

    CPC classification number: H10B12/033 ,  H10B12/31

    Abstract: A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.

    Memory cell, 3D memory and preparation method therefor, and electronic device
    8.
    发明授权
    Memory cell, 3D memory and preparation method therefor, and electronic device 有权

    公开(公告)号：US11825642B1

    公开(公告)日：2023-11-21

    申请号：US18312389

    申请日：2023-05-04

    Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Jin Dai ,  Yong Yu ,  Jing Liang

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    9.
    发明公开
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230171951A1

    公开(公告)日：2023-06-01

    申请号：US17809667

    申请日：2022-06-29

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Guangsu SHAO ,  Deyuan XIAO ,  Yunsong QIU ,  Mengkang YU

    IPC: H01L27/108

    CPC classification number: H01L27/10823 ,  H01L27/10876

    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes a plurality of active pillars, a dielectric layer that is disposed around a circumference of the active pillar and that covers a part of a sidewall of the active pillar, and a word line. Any two adjacent ones of the plurality of active pillars are separated by using a first trench or a second trench. The first trench and the second trench are staggered. The second trench is wider than the first trench. The dielectric layer is disposed around the circumference of the active pillars. The word line partially covers the dielectric layer, and fills a part of the first trench located between adjacent active pillars.

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