公开(公告)号：US20150221568A1

公开(公告)日：2015-08-06

申请号：US14403565

申请日：2013-09-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaodong He

IPC: H01L21/66 ,  H01L23/522 ,  H01L29/78 ,  H01L23/552

CPC classification number: H01L22/34 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/552 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region. The metal shielding layer is used to be connected to the ground terminal of a testing machine during testing, and the first conductivity type and the second conductivity type are opposite conductivity types.

Abstract translation: 本发明提供了用于MOSFET噪声测试的半导体测试结构。 半导体测试结构包括：形成在半导体衬底的第一阱区上的具有第一导电类型的MOSFET器件; 形成在所述MOSFET器件上的金属屏蔽层，所述金属屏蔽层完全覆盖所述MOSFET器件并且延伸超过所述第一阱区域的圆周; 具有第二导电类型的深阱区，形成在靠近第一阱区的底表面的半导体衬底中，深阱区延伸超过第一阱区的圆周; 其中在所述金属屏蔽层的延伸超出所述第一阱区域的部分与所述深阱区域延伸超出所述第一阱区域的部分之间形成垂直通孔，以将所述金属屏蔽层耦合到所述深阱区域。 金属屏蔽层用于在测试期间连接到测试机的接地端子，并且第一导电类型和第二导电类型是相反的导电类型。

公开(公告)号：US20150175409A1

公开(公告)日：2015-06-25

申请号：US14411989

申请日：2013-08-19

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xinwei Zhang ,  Dan Dai ,  Guoping Zhou ,  Changfeng Xia

IPC: B81C1/00

CPC classification number: B81C1/0038 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C1/00531

Abstract: Provided is a method for fabricating a multi-trench structure, including steps of: performing anisotropic etching on a semiconductor substrate so as to form a vertical trench; growing a first epitaxial layer on the semiconductor substrate in which the vertical trench has been formed, so that the first epitaxial layer covers the top of the vertical trench to form a closed structure; performing anisotropic and isotropic etching on the closed structure, so as to form a trench array, and to make the trench array communicate with the vertical trench, the trench array including a number of trenches or vias, upper portions of a number of trenches or vias being separated from each other, and lower portions thereof communicating with each other to form a cavity; and growing a second epitaxial layer to cover the trench array, so as to form a closed multi-trench structure. With two times of growth of the epitaxial layers, the multi-trench structure remains stable and solid in a fabricating process, which prevents phenomena of film breakage or falling off in the fabricating process.

Abstract translation: 提供一种制造多沟槽结构的方法，包括以下步骤：在半导体衬底上进行各向异性蚀刻以形成垂直沟槽; 在其上形成有垂直沟槽的半导体衬底上生长第一外延层，使得第一外延层覆盖垂直沟槽的顶部以形成闭合结构; 在闭合结构上执行各向异性和各向同性蚀刻，以便形成沟槽阵列，并且使沟槽阵列与垂直沟槽连通，沟槽阵列包括多个沟槽或通孔，多个沟槽或通孔的上部 彼此分离，并且其下部彼此连通以形成空腔; 以及生长第二外延层以覆盖沟槽阵列，以便形成封闭的多沟槽结构。 通过外延层的两次生长，多沟槽结构在制造过程中保持稳定和稳定，这防止了制造过程中膜断裂或脱落的现象。

公开(公告)号：US20140147980A1

公开(公告)日：2014-05-29

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: The present invention relates to the technical field of semiconductor manufacturing. A method for manufacturing a semiconductor device is disclosed, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the like.

Abstract translation: 本发明涉及半导体制造技术领域。 公开了一种用于制造半导体器件的方法，其解决了现有技术中在LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件破坏的问题。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 本发明的实施例可应用于BCD处理等。

公开(公告)号：US10254353B2

公开(公告)日：2019-04-09

申请号：US15327956

申请日：2015-06-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Youhui Li ,  Xiaoli Xu

IPC: G01R31/40 ,  G01R19/165 ,  G01R15/04 ,  G06F1/28

Abstract: A brown-out detection circuit having a time sequence control function comprises: a voltage divider (110), a reference voltage source (120), a comparator (130) and a time sequence control module (140); wherein one terminal of the voltage divider (110) is connected to an external power supply, the other terminal of the voltage divider (110) is connected to a positive input of the comparator (130), the reference voltage source (120) is connected to an inverted input of the comparator (130), the time sequence control module (140) is connected to an output of the comparator (130), an output of the time sequence control module (140) serves as an output of the brown-out detection circuit; when a duration of a power supply voltage lower than a reference voltage is not shorter than a preset time, the time sequence control module (140) controls the output of the brown-out detection circuit to be inverted from a high level to a low level.

公开(公告)号：US10084036B2

公开(公告)日：2018-09-25

申请号：US15840791

申请日：2017-12-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Dongfei Zhou ,  Xiaoshe Deng ,  Genyi Wang

IPC: H01L21/338 ,  H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L21/761 ,  H01L29/04 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

公开(公告)号：US10077188B2

公开(公告)日：2018-09-18

申请号：US15405603

申请日：2017-01-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Dan Dai ,  Xinwei Zhang ,  Guoping Zhou ,  Changfeng Xia

IPC: B81C1/00

CPC classification number: B81C1/00825 ,  B81B7/0029 ,  B81C1/0038 ,  B81C2201/0167 ,  B81C2201/053

Abstract: A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO2 on the rear surface of the silicon substrate layer by performing a thermal oxidation process; and depositing a first thin film layer mainly made of silicon nitride on the first oxidation layer by performing a low pressure chemical vapor deposition process.

公开(公告)号：US10019027B2

公开(公告)日：2018-07-10

申请号：US15325855

申请日：2015-06-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Huagang Wu

IPC: G06F1/03 ,  H03L7/16

CPC classification number: G06F1/0321 ,  G06F1/022 ,  H03L7/16

Abstract: A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase lookup table according to the amplitude value (S103); if the second phase is less than the first phase, adjusting and outputting the amplitude value (S105); or else, outputting the original amplitude value (S106); and performing, by a digital-to-analog converter, a digital-to-analog conversion according to the output amplitude value to obtain a sinusoidal wave (S107); wherein, for a N-bit phase accumulation module and a D-bit digital-to-analog converter, the preset phase lookup table has 2D−1-1 phase boundary value records corresponding to 0˜2D−1-2 amplitudes, each phase boundary value is stored in N-2 bits. A direct digital frequency synthesizer applying the above method is also disclosed.

公开(公告)号：US09953970B2

公开(公告)日：2018-04-24

申请号：US15308574

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng Zhang ,  Sen Zhang

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/73 ,  H01L23/535 ,  H01L29/739

CPC classification number: H01L27/027 ,  H01L23/535 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

公开(公告)号：US09905680B2

公开(公告)日：2018-02-27

申请号：US15538450

申请日：2015-09-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/739 ,  H01L29/08

CPC classification number: H01L29/7394 ,  H01L29/0834 ,  H01L29/7393

Abstract: A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

公开(公告)号：US09881994B2

公开(公告)日：2018-01-30

申请号：US14902284

申请日：2014-08-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Dongfei Zhou ,  Xiaoshe Deng ,  Genyi Wang

IPC: H01L21/332 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L21/761 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.