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    AUTONOMOUS POWER AND TIMING SYSTEM
    62.
    发明申请
    AUTONOMOUS POWER AND TIMING SYSTEM 审中-公开

    公开(公告)号：US20170357282A1

    公开(公告)日：2017-12-14

    申请号：US15616553

    申请日：2017-06-07

    Applicant: Integrated Device Technology, Inc.

    Inventor： Richard Maria SCHMITZ

    IPC: G05F3/02

    CPC classification number: G05F3/02

    Abstract: In accordance with aspects of the present invention, and power and timing supply is presented. The supply includes a power supply providing a supply voltage as a function of a load current; and a timing generator providing a frequency signal as a function of the supply voltage, wherein the supply voltage and the frequency signal are within a safe operating range.

    Overvoltage protection circuits and methods of operating same
    63.
    发明授权
    Overvoltage protection circuits and methods of operating same 有权

    公开(公告)号：US09793708B1

    公开(公告)日：2017-10-17

    申请号：US14576288

    申请日：2014-12-19

    Applicant: Integrated Device Technology, Inc.

    Inventor： Alan Wolfram Glaser ,  Tak Kwong Wong ,  Al Fang ,  Roland Thomas Knaack ,  Jon Roderick Williamson

    IPC: H02H9/00 ,  H02H9/04

    CPC classification number: H02H9/042 ,  H02H9/046

    Abstract: Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and second power supply signal lines. This CAS is provided to an input of the voltage clamping circuit, which is electrically coupled to the first power supply signal line and configured to sink current from the first power supply signal line in response to the CAS. The voltage clamping circuit may be configured to turn on and sink current from the first power supply signal line in-sync with a transition of the CAS from a first logic state to a second logic state.

    SYSTEM AND METHOD FOR IMPROVING DICING QUALITY FOR BONDED WAFER PAIRS
    67.
    发明申请
    SYSTEM AND METHOD FOR IMPROVING DICING QUALITY FOR BONDED WAFER PAIRS 审中-公开

    公开(公告)号：US20170170159A1

    公开(公告)日：2017-06-15

    申请号：US14967050

    申请日：2015-12-11

    Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

    Inventor： Srikanth Kulkarni ,  Viresh P. Patel

    IPC: H01L25/00 ,  H01L21/78

    CPC classification number: H01L25/50 ,  H01L21/78

    Abstract: A method for manufacturing a plurality of die pairs includes providing a first wafer including a plurality of spaced apart first dies arranged in a first array including a first, first die row and a second, first die row spaced apart by a first portion of a first row channel; providing a second wafer including a plurality of spaced apart second dies arranged in a second array including a first, second die row and a second, second die row spaced apart by a second portion of the first row channel; connecting the first wafer to the second wafer with a connector assembly to form a wafer pair such that the first dies and the second dies cooperate to form the plurality of die pairs; positioning a first support assembly between the first wafer and the second wafer to rigidly support the first wafer relative to the second wafer; and cutting along the first row channel with a blade to separate the plurality of die pairs from one another.

    Calibration method and apparatus for phase locked loop circuit
    69.
    发明授权
    Calibration method and apparatus for phase locked loop circuit 有权

    公开(公告)号：US09654121B1

    公开(公告)日：2017-05-16

    申请号：US15169997

    申请日：2016-06-01

    Applicant: Integrated Device Technology, Inc.

    Inventor： Min Chu

    IPC: H03L7/06 ,  H03L7/099

    CPC classification number: H03L7/0992 ,  H03L7/099 ,  H03L2207/06 ,  H03L2207/50

    Abstract: An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal. The calibration circuit also includes a selection block for performing a convergence test using the counted number of fast clock cycles, N, and M. The selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.

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