公开(公告)号：US20190065097A1

公开(公告)日：2019-02-28

申请号：US15798370

申请日：2017-10-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Hsien Liu ,  Chien-Han Kuo

IPC: G06F3/06

Abstract: A data storage method is provided according to an exemplary embodiment of the disclosure. The method is configured for a rewritable non-volatile memory module. The method includes: performing a data merge operation; adjusting a data receiving amount per unit time for receiving to-be-written data from a host system according to a data storage state of the rewritable non-volatile memory module; storing the received to-be-written data into a buffer memory during the data merge operation being performed; and storing the data stored in the buffer memory into the rewritable non-volatile memory module.

公开(公告)号：US10203886B2

公开(公告)日：2019-02-12

申请号：US15080557

申请日：2016-03-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jia-Yan Huang

IPC: G06F12/00 ,  G06F3/06

Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: determining whether receiving a predetermined command from a host system. The method also includes: if receiving the predetermined command from the host system, writing at least one buffer data from a buffer memory into a first physical erasing unit, selecting at least one second physical erasing unit from the physical erasing units, and writing at least one valid data of the at least one second physical erasing unit into the first physical erasing unit in response to the predetermined command.

公开(公告)号：US20190034329A1

公开(公告)日：2019-01-31

申请号：US15706765

申请日：2017-09-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0679

Abstract: An exemplary embodiment of the disclosure provides a data storage method for a rewritable non-volatile memory module. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit of a first management unit and not storing the first data to the rewritable non-volatile memory module if a data content of the first data is identical to a data content of second data, and the second data is stored in the first physical unit; and storing logical-to-physical bit map information to a second physical unit in the first management unit, and the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit.

公开(公告)号：US10193569B2

公开(公告)日：2019-01-29

申请号：US14477867

申请日：2014-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Fu Tseng ,  Tsai-Cheng Lin ,  Yen-Chiao Lai

IPC: H03M13/11 ,  H04L1/00 ,  H03M13/25 ,  G06F11/07 ,  H03M13/37 ,  H03M13/29

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.

公开(公告)号：US10193537B2

公开(公告)日：2019-01-29

申请号：US15487417

申请日：2017-04-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Bing-Wei Yi

IPC: H03K3/012 ,  H03K3/84 ,  H03K5/159 ,  H03K5/19 ,  G11C7/24 ,  G06F7/58 ,  G11C7/22 ,  H03K19/21 ,  G11C27/02

Abstract: An exemplary embodiment of the disclosure provides a random data generation circuit which includes a phase difference detection circuit and a random data output circuit. The phase difference detection circuit detects a phase difference between a first clock signal and a second clock signal and outputs phase difference information. The random data output circuit is coupled to the phase difference detection circuit and outputs random data according to the phase difference information. Thereby, ideal and unpredictable random data is generated.

公开(公告)号：US20190012080A1

公开(公告)日：2019-01-10

申请号：US15690286

申请日：2017-08-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Wen Chen ,  Che-Yueh Kuo

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory management method is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a valid data parameter based on a valid data amount of valid data stored in a plurality of physical erasing units, and obtaining a first threshold value based on the valid data parameter. The method also includes: obtaining a first determination parameter based on a number of a plurality of first physical erasing units, and the first physical erasing units are physical erasing units being programmed for storing data by using a single-page programming mode. The method further includes: performing a garbage collection operation if the first determination parameter is greater than the first threshold value.

公开(公告)号：US10152426B2

公开(公告)日：2018-12-11

申请号：US15183813

申请日：2016-06-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G06F12/1009

Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.

公开(公告)号：US10102121B1

公开(公告)日：2018-10-16

申请号：US15649655

申请日：2017-07-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/06 ,  G06F12/02

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: configuring a plurality of first type super physical units and at least one second type super physical unit, where one first type super physical unit includes at least two available physical erasing units which may be programmed simultaneously, and one second type super physical unit includes at least two available physical erasing units which may not be programmed simultaneously. The method also includes: configuring the first type super physical unit as to be programmed based on a first programming mode or a second programming mode, and configuring the second type super physical unit as to be programmed only based on the first programming mode.

公开(公告)号：US20180260317A1

公开(公告)日：2018-09-13

申请号：US15973548

申请日：2018-05-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Hua Chu

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7205

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a first write command from a host system and writing a first data indicated by the first write command to a physical erasing unit which is currently served as a receiving physical erasing unit; and copying valid data from a first physical erasing unit and writing the valid data to a physical erasing unit which is currently served as a recycling physical erasing unit in a garbage collection operation, where the physical erasing unit currently served as the receiving physical erasing unit and the physical erasing unit currently served as the recycling physical erasing unit are two physical erasing units independent from each other.

公开(公告)号：US20180210478A1

公开(公告)日：2018-07-26

申请号：US15460245

申请日：2017-03-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Bing-Wei Yi

IPC: G05F1/575 ,  G11C16/32 ,  G11C16/28 ,  G11C16/16

CPC classification number: G05F1/575 ,  G11C5/143 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

Abstract: An exemplary embodiment of the disclosure provides a reference voltage generation circuit which includes a unit switch circuit and a voltage output circuit. The unit switch circuit is configured to receive a control voltage and generate a plurality of base voltages on a detection point inside the reference voltage generation circuit. The voltage output circuit is coupled to the unit switch circuit and is configured to modify a reference voltage for generating a specific voltage according to the base voltages. Therefore, an influence on the reference voltage due to process variation can be reduced.