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公开(公告)号：US20190155328A1
公开(公告)日：2019-05-23
申请号：US16165978
申请日：2018-10-19
Applicant: Graphcore Limited
Inventor： Simon Christian Knowles , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix , Jonathan Mangnall , David Lacey
Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient processing unit executes a switch control instruction from its local program to control its switching circuitry to connect its input set of wires to the switching fabric to receive the data packet at a receive time, the transmit time and, switch time and receive time being governed by the common clock with respect to the synchronisation signal.
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公开(公告)号：US20190121777A1
公开(公告)日：2019-04-25
申请号：US15886131
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Simon Christian Knowles , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix , Jonathan Mangnall , David Lacey
IPC: G06F15/173 , G06F15/80 , G06F8/41 , G06F9/38
Abstract: The invention relates to a computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising one or more computer executable instruction which, when executed, implements: a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time; and a switch control function which causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined receive time.
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公开(公告)号：US20190121387A1
公开(公告)日：2019-04-25
申请号：US15886009
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Simon Christian Knowles , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix , Jonathan Mangnall , David Lacey
Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient processing unit executes a switch control instruction from its local program to control its switching circuitry to connect its input set of wires to the switching fabric to receive the data packet at a receive time, the transmit time and, switch time and receive time being governed by the common clock with respect to the synchronisation signal.
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公开(公告)号：US12141092B2
公开(公告)日：2024-11-12
申请号：US17658124
申请日：2022-04-06
Applicant: Graphcore Limited
Inventor： Simon Christian Knowles , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix , Jonathan Mangnall , David Lacey
IPC: G06F15/173 , G06F8/41 , G06F9/38 , G06F15/80
Abstract: The invention relates to a computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising one or more computer executable instruction which, when executed, implements: a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time; and a switch control function which causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined receive time.
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公开(公告)号：US12140629B2
公开(公告)日：2024-11-12
申请号：US17814396
申请日：2022-07-22
Applicant: Graphcore Limited
Inventor： Stephen Felix , Natalie Narkonski , Philip Horsfield
IPC: G01R31/3185
Abstract: A method for repairing a processor. The processor comprises a plurality of processing units and an exchange comprising a plurality of exchange paths for transmitting data between the processing units. Each processing unit is connected to output data to a respective exchange path. An exchange path functional test of at least a portion of the exchange paths is carried out. Based on the exchange path functional test, it is identified that one or more of the exchange paths is defective, and the processing units connected to the one or more defective exchange paths is identified. The identified processing units are switched out of functional operation of the processor and switching in at least one repair processing unit connected to a non-defective exchange path for functional operation of the processor.
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Patent Agency Ranking
公开(公告)号：US12001263B2
公开(公告)日：2024-06-04
申请号：US18295921
申请日：2023-04-05
Applicant: Graphcore Limited
Inventor： Stephen Felix , Mrudula Gore
IPC: G06F1/324 , G06F1/06 , G06F1/08 , G06F1/3206
CPC classification number: G06F1/324 , G06F1/06 , G06F1/08 , G06F1/3206
Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.
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67.发明授权公开(公告)号：US11900109B2
公开(公告)日：2024-02-13
申请号：US15886331
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Stephen Felix , Simon Christian Knowles , Godfrey Da Costa
CPC classification number: G06F9/30036 , G06F9/30018
Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which, when executed by the execution unit, masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and symbols in place of the selected values.
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公开(公告)号：US11726937B2
公开(公告)日：2023-08-15
申请号：US17447832
申请日：2021-09-16
Applicant: Graphcore Limited
Inventor： Graham Bernard Cunningham , Stephen Felix
IPC: G06F13/364 , G06F9/52 , G06F13/40
CPC classification number: G06F13/364 , G06F9/522 , G06F13/4059
Abstract: A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.
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69.发明授权公开(公告)号：US11698883B2
公开(公告)日：2023-07-11
申请号：US17345290
申请日：2021-06-11
Applicant: Graphcore Limited
Inventor： Stephen Felix , Jonathan Mangnall
CPC classification number: G06F15/80 , G06F11/2028
Abstract: A method of recording tile identifiers in each of a plurality of tiles of a multitile processor is described. Tiles are arranged in columns, each column having a plurality of processing circuits, each processing circuit comprising one or more tiles, wherein a base processing circuit in each column is connected to a set of processing circuit identifier wires. A base value is generated on each of the set of processing circuit identifier wires for the base processing circuit in each column. At the base processing circuit, the base value on the set of processing circuit identifier wires is read and incremented by one. The incremented value is propagated to a next processing circuit in the column, and at the next processing circuit a unique identifier is recorded by concatenating an identifier of the column and the incremented value.
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公开(公告)号：US11644884B2
公开(公告)日：2023-05-09
申请号：US17445219
申请日：2021-08-17
Applicant: Graphcore Limited
Inventor： Stephen Felix , Mrudula Gore
IPC: G06F1/324 , G06F1/06 , G06F1/08 , G06F1/3206
CPC classification number: G06F1/324 , G06F1/06 , G06F1/08 , G06F1/3206
Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.
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