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公开(公告)号：US11334320B2
公开(公告)日：2022-05-17
申请号：US16797582
申请日：2020-02-21
Applicant: Graphcore Limited
Inventor： Stephen Felix , Godfrey Da Costa
Abstract: An execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.
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公开(公告)号：US20230185880A1
公开(公告)日：2023-06-15
申请号：US18066627
申请日：2022-12-15
Applicant: Graphcore Limited
Inventor： Godfrey Da Costa , Badreddine Noune , Daniel Justus , Carlo Luschi
IPC: G06F18/211 , G06F18/21 , G06F18/22 , G06N3/04
CPC classification number: G06F18/211 , G06F18/217 , G06F18/22 , G06N3/04
Abstract: A computer-implemented method comprising: processing data in a neural network to compute a network tensor comprising a plurality of tensor elements represented in an initial numerical format; computing a histogram of tensor elements; selecting a target numerical format, the target numerical format having a lower precision than the initial numerical format; evaluating a metric based on the histogram of tensor elements and the target numerical format, the metric indicating a degree of accuracy of a representation of the network tensor in the target numerical format; and based on the evaluated metric, converting the plurality of tensor elements from the initial numerical format to the target numerical format.
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公开(公告)号：US20190121616A1
公开(公告)日：2019-04-25
申请号：US15886505
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Stephen Felix , Godfrey Da Costa
Abstract: The present relates to invention deals with an execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.
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公开(公告)号：US20190121639A1
公开(公告)日：2019-04-25
申请号：US15886331
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Stephen Felix , Simon Christian Knowles , Godfrey Da Costa
Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which when executed by the execution unit masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and the masked values in their respective original locations.
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公开(公告)号：US11762641B2
公开(公告)日：2023-09-19
申请号：US17110834
申请日：2020-12-03
Applicant: Graphcore Limited
Inventor： Godfrey Da Costa , Timothy David Hutt
IPC: G06F8/41
CPC classification number: G06F8/45 , G06F8/445 , G06F8/4434
Abstract: A method of allocating variables to computer memory includes determining at compile time when each of the plurality of variables is live in a memory region and allocating a memory region to each variable wherein at least some variables are allocated at compile time to overlapping memory regions to be stored in those memory regions at runtime at non-overlapping times.
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Patent Agency Ranking
公开(公告)号：US20230186095A1
公开(公告)日：2023-06-15
申请号：US18066530
申请日：2022-12-15
Applicant: Graphcore Limited
Inventor： Godfrey Da Costa , Badreddine Noune , Daniel Justus , Carlo Luschi
IPC: G06N3/084
CPC classification number: G06N3/084
Abstract: A computer-implemented method of training a multi-layer neural network comprising a set of network weights, comprising: processing the training data in respective forward and backward passes through multiple layers, the forward pass comprising computing a set of activations in dependence on the network weights and training data, and the backward pass comprising: computing gradients of a pre-determined loss function with respect to the network weights and/or activations, wherein an adjustment parameter is applied to at least a subset of values in the neural network, the values comprising at least one of: the network weights, the activations, the gradients with respect to activations and the gradients with respect to weights; updating the network weights in dependence on the computed gradients; computing a proportion of the subset of values falling above a predefined threshold; and updating the adjustment parameter in dependence on the computed proportion.
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公开(公告)号：US20200319861A1
公开(公告)日：2020-10-08
申请号：US16527410
申请日：2019-07-31
Applicant: Graphcore Limited
Inventor： David Lacey , Godfrey Da Costa
IPC: G06F8/41
Abstract: A method for generating an executable program to run on one or more processor modules. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and edges; and compiling the graph into an executable program including one or more types of multi-access instruction each of which performs at least two memory access (load and/or store) operations in a single instruction. The memory on each processor module comprises multiple memory banks whereby the same bank cannot be accessed by different load or store operations in the same instruction. The compilation comprises assigning instances of the multi-access instructions to implement at least some of the graph edges, and allocating the data to memory addresses within different ones of the banks. The allocating is performed subject to one or more constraints, including at least that different load/store operations should not access the same memory bank in the same instruction.
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公开(公告)号：US12112164B2
公开(公告)日：2024-10-08
申请号：US18176034
申请日：2023-02-28
Applicant: Graphcore Limited
Inventor： Alan Alexander , Simon Knowles , Godfrey Da Costa , Badreddine Noune
IPC: G06F9/30
CPC classification number: G06F9/30014 , G06F9/3013
Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.
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9.发明授权公开(公告)号：US11900109B2
公开(公告)日：2024-02-13
申请号：US15886331
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Stephen Felix , Simon Christian Knowles , Godfrey Da Costa
CPC classification number: G06F9/30036 , G06F9/30018
Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which, when executed by the execution unit, masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and symbols in place of the selected values.
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公开(公告)号：US20230281013A1
公开(公告)日：2023-09-07
申请号：US18176034
申请日：2023-02-28
Applicant: Graphcore Limited
Inventor： Alan ALEXANDER , Simon KNOWLES , Godfrey Da Costa , Badreddine NOUNE
IPC: G06F9/30
CPC classification number: G06F9/30014 , G06F9/3013
Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.
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