公开(公告)号：US12120865B2

公开(公告)日：2024-10-15

申请号：US17132981

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

CPC classification number: H10B12/30 ,  H01L21/6835 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B53/30 ,  H01L2221/68363

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US12114479B2

公开(公告)日：2024-10-08

申请号：US17368329

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H10B12/00 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/786

CPC classification number: H10B12/31 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L29/78696 ,  H10B12/30

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US12058847B2

公开(公告)日：2024-08-06

申请号：US16888910

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek A. Sharma ,  Charles Kuo ,  Brian S. Doyle ,  Urusa Shahriar Alaan ,  Van H Le ,  Elijah V. Karpov ,  Kaan Oguz ,  Arnab Sen Gupta

IPC: H10B12/00 ,  H01L25/065

CPC classification number: H10B12/30 ,  H01L25/0657

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240088017A1

公开(公告)日：2024-03-14

申请号：US17930825

申请日：2022-09-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40

Abstract: Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.

公开(公告)号：US20240071955A1

公开(公告)日：2024-02-29

申请号：US17899670

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Shem Ogadhoh ,  Swaminathan Sivakumar ,  Sagar Suthram ,  Elliot Tan

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/085

CPC classification number: H01L23/564 ,  H01L23/528 ,  H01L27/085

Abstract: Described herein is full wafer device that includes a computing logic formed over a substrate and two directional indicators formed in the substrate. The computing logic is arranged as a plurality of dies having a first die edge direction and a second die edge direction perpendicular to the first die edge direction. The computing logic further includes an angled feature extending in a feature direction, the feature direction different from the first die edge direction and the second die edge direction. The first directional indicator formed in the substrate indicates the first die edge direction. The second directional indicator formed in the substrate indicates the feature direction.

公开(公告)号：US11888034B2

公开(公告)日：2024-01-30

申请号：US16435358

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ashish Agarwal ,  Urusa Alaan ,  Christopher Jezewski ,  Kevin Lin ,  Carl Naylor

IPC: H01L29/26 ,  H01L29/51 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L29/26 ,  H01L27/092 ,  H01L29/16 ,  H01L29/517

Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

公开(公告)号：US20240030213A1

公开(公告)日：2024-01-25

申请号：US18474275

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2924/01014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L23/53223

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US20230422496A1

公开(公告)日：2023-12-28

申请号：US18314862

申请日：2023-05-10

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Rishabh Mehandru

IPC: H10B41/27 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H10B41/35 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L23/5283 ,  H01L23/5226 ,  H10B41/35 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nanoribbon) of one or more semiconductor materials extending between a first side (e.g., a back side) and an opposing second side (e.g., a front side) of a substrate. The first S/D region of the transistor may be provided at the first side of the substrate, while the second S/D region of the transistor may be provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. Implementing various logic circuits using vertical transistors with backside S/D regions may provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

公开(公告)号：US20230420432A1

公开(公告)日：2023-12-28

申请号：US17846173

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  G02B6/42

CPC classification number: H01L25/167 ,  H01L24/08 ,  H01L23/3107 ,  H01L24/80 ,  H01L24/94 ,  G02B6/4298 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.