公开(公告)号：US20200219986A1

公开(公告)日：2020-07-09

申请号：US16242670

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Glenn A. Glass ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/40 ,  H01L29/778 ,  H01L21/265

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

公开(公告)号：US10192969B2

公开(公告)日：2019-01-29

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L23/535 ,  H01L23/66 ,  H01L21/3115

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US09947585B2

公开(公告)日：2018-04-17

申请号：US15127839

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Rahul Ramaswamy

IPC: H01L29/78 ,  H01L29/76 ,  H01L27/088 ,  H01L21/283 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42368 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.

公开(公告)号：US09741721B2

公开(公告)日：2017-08-22

申请号：US14912890

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Joodong Park ,  Gopinath Bhimarasetti ,  Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.